參數(shù)資料
型號： TMS320LC2402APG
廠商： Texas Instruments, Inc.
英文描述： Foot Grounder; Features:1 megohm resistor; elastic strap for comfort; elastic velcro; D-ring adjustability; 3 layer sole for durability; 18" conductive ribbon RoHS Compliant: NA
中文描述： DSP控制器
文件頁數(shù)： 17/133頁
文件大?。?/td> 1672K
代理商： TMS320LC2402APG
SPRS145J JULY 2000 REVISED NOVEMBER 2004
17
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
pin functions (continued)
Table 2. LF240xA and LC240xA Pin List and Package Options
(Continued)
PIN NAME
LF2407A
(144-PGE)
2406A
(100-PZ)
LC2404A
(100-PZ)
2403A,
LC2402A
(64-PAG)
and
2402A
(64-PG)
DESCRIPTION
ADDRESS, DATA, AND MEMORY CONTROL SIGNALS (CONTINUED)
IS
82
I/O space strobe. IS, DS, and PS are always high
unless low-level asserted for access to the
relevant external memory space or I/O. They are
placed in the high-impedance state.
PS
84
Program space strobe. IS, DS, and PS are always
high unless low-level asserted for access to the
relevant external memory space or I/O. They are
placed in the high-impedance state.
R/W
92
Read/write qualifier signal. R/W indicates transfer
direction during communication to an external
device. It is normally in read mode (high), unless
low level is asserted for performing a write
operation. R/W is placed in the high-impedance
state.
W/R
/ IOPC0
W/R
19
Write/Read qualifier or GPIO. This is an inverted
R/W signal useful for zero-wait-state memory
interface. It is normally low, unless a memory write
operation is performed.
See Table 12, Port C
section, for reset note regarding LF2406A and
LF2402A.
(
↑
)
Read-enable strobe. Read-select indicates an
active, external read cycle. RD is active on all
external program, data, and I/O reads. RD is
placed in the high-impedance state.
IOPC0
19
14
14
RD
93
WE
89
Write-enable strobe. The falling edge of WE
indicates that the device is driving the external
data bus (D15D0). WE is active on all external
program, data, and I/O writes. WE is placed in the
high-impedance state.
STRB
96
External memory access strobe. STRB is always
high unless asserted low to indicate an external
bus cycle. STRB is active for all off-chip
accesses. STRB is placed in the high-impedance
state.
Bold, italicized pin names
indicate pin function after reset.
GPIO General-purpose input/output pin. All GPIOs come up as input after reset.
§It is highly recommended that VCCA be isolated from the digital supply voltage (and VSSA from digital ground) to maintain the specified accuracy
and improve the noise immunity of the ADC.
Only when all of the following conditions are met: EMU1/OFF is low, TRST is low, and EMU0 is high
#No power supply pin (VDD, VDDO, VSS, or VSSO) should be left unconnected. All power supply pins must be connected appropriately for proper
device operation.
LEGEND:
↑
Internal pullup
↓
Internal pulldown
(Typical active pullup/pulldown value is
±
16
μ
A.)
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