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參數(shù)資料
| 型號： | TMS320F243PGEQ |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 16-Bit Digital Signal Processor |
| 中文描述： | 16位數(shù)字信號處理器 |
| 文件頁數(shù)： | 44/116頁 |
| 文件大?。?/td> | 1485K |
| 代理商： | TMS320F243PGEQ |
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TMS320F243, TMS320F241
DSP CONTROLLERS
SPRS064B – DECEMBER 1997 – REVISED FEBRUARY 1999
44
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
internal memory (continued)
dual-access RAM (DARAM)
There are 544 words
×
16 bits of DARAM on the ’x243/’x241 device. The ’x243/’x241 DARAM allows writes to
and reads from the RAM in the same cycle. The DARAM is configured in three blocks: block 0 (B0), block 1 (B1),
and block 2 (B2). Block 1 contains 256 words and Block 2 contains 32 words, and both blocks are located only
in data memory space. Block 0 contains 256 words, and can be configured to reside in either data or program
memory space. The SETC CNF (configure B0 as data memory) and CLRC CNF (configure B0 as program
memory) instructions allow dynamic configuration of the memory maps through software.
When using on-chip RAM, or high-speed external memory, the ’x243/’x241 runs at full speed with no wait states.
The ability of the DARAM to allow two accesses to be performed in one cycle, coupled with the parallel nature
of the ’x243/’x241 architecture, enables the device to perform three concurrent memory accesses in any given
machine cycle. Externally, the READY line can be used to interface the ’x243/’x241 to slower, less expensive
external memory. Downloading programs from slow off-chip memory to on-chip RAM can speed processing
while cutting system costs.
flash EEPROM
Flash EEPROM provides an attractive alternative to masked program ROM. Like ROM, flash is nonvolatile.
However, it has the advantage of “in-target” reprogrammability. The ’F243/’F241 incorporates one 8K
flash EEPROM module in program space. This type of memory expands the capabilities of the ’F243/’F241 in
the areas of prototyping, early field-testing, and single-chip applications.
16-bit
Unlike most discrete flash memory, the ’F243/’F241 flash does not require a dedicated state machine, because
the algorithms for programming and erasing the flash are executed by the DSP core. This enables several
advantages, including: reduced chip size and sophisticated, adaptive algorithms. For production programming,
the IEEE Standard 1149.1
(JTAG) scan port provides easy access to the on-chip RAM for downloading the
algorithms and flash code. Other key features of the flash include zero-wait-state access rate and single 5-V
power supply. Before programming, the flash EEPROM module generates the necessary voltages internally,
making it unnecessary to provide the programming or erase voltages externally.
An erased bit in the flash is read as a logic 1, and a programmed bit is read as a logic 0. The flash requires a
block-erase of the entire 8K module; however, any combination of bits can be programmed. The following four
algorithms are required for flash operations: clear, erase, flash-write, and program. For an explanation of these
algorithms and a complete description of the flash EEPROM, see the TMS320F20x/F24x DSP Embedded Flash
Memory Technical Reference(literature number SPRU282).
flash serial loader/utilities
The on-chip flash is shipped with a serial bootloader code programmed at the following addresses:
0000–00FFh. All other flash memory locations are in an erased state. The serial bootloader can be used to load
flash-programming algorithms or code to any destination RAM through the on-chip serial communications
interface (SCI). Refer to the TMS320F240 Serial Bootloader application note (located at
ftp://www.ti.com/
) to
understand on-chip flash programming using the serial bootloader code. (Choose
/pub/tms320bbs/c24xfiles
at the main ftp directory to locate the
f240boot.pdf
file.) The latest TMS320F243/241 flash utilities should be
available at
http://www.ti.com
which is the external TI web site.
IEEE Standard 1149.1–1990, IEEE Standard Test Access Port.
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| TMS320C6454GTZ | Fixed-Point Digital Signal Processor |
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