參數(shù)資料
型號： TMS320F243PGEQ
元件分類： 數(shù)字信號處理
英文描述： 16-Bit Digital Signal Processor
中文描述： 16位數(shù)字信號處理器
文件頁數(shù)： 14/116頁
文件大小： 1485K
代理商： TMS320F243PGEQ
TMS320F243, TMS320F241
DSP CONTROLLERS
SPRS064B – DECEMBER 1997 – REVISED FEBRUARY 1999
14
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
Terminal Functions - ’F241 PG and FN Packages
NAME
64
QFP
NO.
68
PLCC
NO.
TYPE
RESET
STATE
DESCRIPTION
INTERFACE CONTROL SIGNALS
VCCP/WDDIS
52
63
I
I
Flash programming voltage supply pin. This is the 5-V supply used for
flash programming. Flash cannot be programmed if this pin is held at 0 V.
This pin also works as a hardware watchdog disable, when VCCP/WDDIS
= +5 V and bit 6 in WDCR is set to 1. Note that on ROM devices, only the
WDDIS function is valid.
ANALOG-TO-DIGITAL CONVERTER (ADC) INPUTS
ADCIN00
24
32
ADCIN01
23
31
ADCIN02
22
30
ADCIN03
21
29
I
I
Analog inputs to the ADC
ADCIN04
20
28
ADCIN05
19
26
ADCIN06
18
25
ADCIN07
15
22
VCCA
14
21
–
–
Analog supply voltage for ADC (5 V). VCCA must be isolated from digital
supply voltage.
VSSA
VREFHI
VREFLO
13
20
–
–
Analog ground reference for ADC
16
23
–
–
ADC analog high-voltage reference input
17
24
–
–
ADC analog low-voltage reference input
EVENT MANAGER
Timer 1 compare output/general-purpose bidirectional digital I/O (GPIO).
T1CMP/T1PWM/
IOPB4
T2CMP/T2PWM/
IOPB5
12
19
I/O/Z
11
18
I/O/Z
Timer 2 compare output/GPIO
TDIR/
IOPB6
56
67
I/O
Counting direction for GP timer/GPIO. If TDIR=1, upward counting is
selected. If TDIR=0, downward counting is selected.
TCLKIN/
IOPB7
57
68
I/O
External clock input for GP timer/GPIO. Note that timer can also use the
internal device clock.
CAP1/QEP0/
IOPA3
CAP2/QEP1/
IOPA4
CAP3/
IOPA5
PWM1/
IOPA6
PWM2/
IOPA7
PWM3/
IOPB0
PWM4/
IOPB1
PWM5/
IOPB2
PWM6/
IOPB3
8
15
I/O
Capture input #1/quadrature encoder pulse input #0/GPIO
7
14
I/O
I
Capture input #2/quadrature encoder pulse input #1/GPIO
6
13
I/O
Capture input #3/GPIO
64
7
I/O/Z
Compare/PWM output pin #1 or GPIO
63
6
I/O/Z
Compare/PWM output pin #2 or GPIO
62
5
I/O/Z
Compare/PWM output pin #3 or GPIO
61
4
I/O/Z
Compare/PWM output pin #4 or GPIO
60
3
I/O/Z
Compare/PWM output pin #5 or GPIO
59
2
I/O/Z
Compare/PWM output pin #6 or GPIO
PDPINT§
58
1
I
I
Power drive protection interrupt input. This interrupt, when activated, puts
the PWM output pins in the high-impedance state, should motor
drive/power converter abnormalities, such as overvoltage or overcurrent,
etc., arise. PDPINT is a falling-edge-sensitive interrupt. After the falling
edge, this pin must be held low for two clock cycles for the core to
recognize the interrupt.
I = input, O = output, Z = high impedance
The reset state indicates the state of the pin at reset. If the pin is an input, indicated by an I, its state is determined by user design. If the pin is
an output, its level at reset is indicated.
§ In silicon revisions 2.0-TMX and 2.1-TMS, this pin is level-sensitive and can cause multiple interrupts when held low.
NOTE:
Bold, italicized pin names
indicate pin function after reset.
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