參數(shù)資料
型號： TMS320F243PGEQ
元件分類： 數(shù)字信號處理
英文描述： 16-Bit Digital Signal Processor
中文描述： 16位數(shù)字信號處理器
文件頁數(shù)： 35/116頁
文件大?。?/td> 1485K
代理商： TMS320F243PGEQ
TMS320F243, TMS320F241
DSP CONTROLLERS
SPRS064B – DECEMBER 1997 – REVISED FEBRUARY 1999
35
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
low-power modes (continued)
Two control bits, LPM(1) and LPM(0), specify which of the three possible low-power modes is entered when
the IDLE instruction is executed (see Table 12). These bits are located in the System Control and Status
Register (SCSR) described in the TMS320C241/C242/C243 DSP Controllers CPU, System, Instruction Set,
and Peripherals Reference Guide (literature number SPRU276).
Table 12. Low-Power Modes Summary
LOW-POWER MODE
LPMx BITS
SCSR[12:13]
CPU
CLOCK
DOMAIN
SYSTEM
CLOCK
DOMAIN
WDCLK
STATUS
PLL
STATUS
OSC
STATUS
EXIT
CONDITION
CPU running normally
XX
On
On
On
On
On
—
IDLE1 – (LPM0)
00
Off
On
On
On
On
Peripheral Interrupt,
External Interrupt,
Reset
IDLE2 – (LPM1)
01
Off
Off
On
On
On
Wakeup Interrupts,
External Interrupt,
Reset
HALT – (LPM2)
{PLL/OSC power down}
1X
Off
Off
Off
Off
Off
Reset Only
wakeup from low-power modes
reset
A reset (from any source) causes the device to exit any of the IDLE modes. If the device is halted, the reset will
first start the oscillator, and there can be a delay while the oscillator powers up before clocks are generated to
initiate the CPU reset sequence.
external interrupts
The external interrupts, XINTx, can cause the device to exit any of the low-power modes, except HALT. If the
device is in IDLE2 mode, the synchronous logic connected to the external interrupt pins is bypassed with
combinatorial logic which recognizes the interrupt on the pin, starts the clocks, and then allows the clocked logic
to generate an interrupt request to the PIE controller. Note that in Table 12, external interrupts include PDPINT.
wakeup interrupts
Certain peripherals (for example, the CAN wakeup interrupt which can assert the CAN error interrupt request
even when there are no clocks running) can have the capability to start the device clocks and then generate
an interrupt in response to certain external events, for example, activity on a communication line.
peripheral interrupts
All peripheral interrupts, if enabled locally and globally, can cause the device to exit IDLE1 mode.
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