參數(shù)資料
型號(hào)： TMS320F243PGEQ
元件分類： 數(shù)字信號(hào)處理
英文描述： 16-Bit Digital Signal Processor
中文描述： 16位數(shù)字信號(hào)處理器
文件頁數(shù)： 27/116頁
文件大小： 1485K
代理商： TMS320F243PGEQ
TMS320F243, TMS320F241
DSP CONTROLLERS
SPRS064B – DECEMBER 1997 – REVISED FEBRUARY 1999
27
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
reset
The reset operation ensures an orderly startup sequence for the device. There are two possible causes of a
reset, as shown in Figure 5.
Signal
Reset
System Reset
Watchdog Timer Reset
External Reset (RS) Pin Active
Figure 5. Reset Signals
The two possible reset signals are generated as follows:
Watchdog timer reset.
A watchdog-timer-generated reset occurs if the watchdog timer overflows or an
improper value is written to either the watchdog key register or the watchdog control register. (Note that
when the device is powered on, the watchdog timer is automatically active.) The watchdog timer reset is
reflected on the external RS pin also.
Reset pin active.
To generate an external reset pulse on the RS pin, a low-level pulse duration of at least
one CPUCLK cycle is necessary to ensure that the device recognizes the reset signal.
Once watchdog reset is activated, the external RS pin is driven (active) low for a minimum of eight CPUCLK
cycles. This allows the TMS320x24x device to reset external system components.
The occurrence of a reset condition causes the TMS320x24x to terminate program execution and affects
various registers and status bits. During a reset, RAM contents remain unchanged, and all control bits that are
affected by a reset are initialized to their reset state.
hardware-generated interrupts
The ’24x CPU supports one nonmaskable interrupt (NMI) and six maskable prioritized interrupt requests. The
’24x devices have many peripherals, and each peripheral is capable of generating one or more interrupts in
response to many events. The ’24x CPU does not have sufficient interrupt requests to handle all these
peripheral interrupt requests; therefore, a centralized interrupt controller is provided to arbitrate the interrupt
requests from all the different sources. Throughout this section, refer to Figure 6 .
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