參數(shù)資料
型號： TMS320F241PGQ
元件分類： 數(shù)字信號處理
英文描述： 16-Bit Digital Signal Processor
中文描述： 16位數(shù)字信號處理器
文件頁數(shù)： 33/116頁
文件大小： 1485K
代理商： TMS320F241PGQ
TMS320F243, TMS320F241
DSP CONTROLLERS
SPRS064B – DECEMBER 1997 – REVISED FEBRUARY 1999
33
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
interrupt operation sequence (continued)
1.
The PIE controller decodes the PAB value and generates an internal peripheral interrupt acknowledge to
load the PIV into the PIVR. The appropriate peripheral interrupt vector (or the phantom interrupt vector),
is referenced from the table stored in the PIE controller.
2.
When the GISR has completed any necessary context saves, it reads the PIVR and uses the interrupt vector
as a target (or to generate a target) for a branch to the Event-Specific Interrupt Service Routine (SISR) for
the interrupt event which occurred in the peripheral. Interrupts must notbe re-enabled until the PIVR has
been read; otherwise, its contents can get overwritten by a subsequent interrupt.
external interrupts
The ’F243/’F241 devices have four external interrupts. These interrupts include:
XINT1.
The XINT1 control register (at 7070h) provides control and status for this interrupt. XINT1 can be used
as a high-priority (Level 1) or low-priority (Level 6) maskable interrupt or as a general-purpose I/O pin. XINT1
can also be programmed to trigger an interrupt on either the rising or the falling edge.
XINT2.
The XINT2 control register (at 7071h) provides control and status for this interrupt. XINT2 can be used
as a high-priority (Level 1) or low-priority (Level 6) maskable interrupt or a general-purpose I/O pin. XINT2 can
also be programmed to trigger an interrupt on either the rising or the falling edge.
NMI.
This is a nonmaskable external interrupt.
PDPINT.
This interrupt is provided for safe operation of power converters and motor drives controlled by
the ’F243/’F241. This maskable interrupt can put the timers and PWM output pins in high-impedance states
and inform the CPU in case of motor drive abnormalities such as overvoltage, overcurrent, and excessive
temperature rise. PDPINT is a Level 1 interrupt.
Table 11 is a summary of the external interrupt capability of the ’F243/’F241.
Table 11. External Interrupt Types and Functions
EXTERNAL
INTERRUPT
CONTROL
REGISTER
NAME
CONTROL
REGISTER
ADDRESS
MASKABLE
XINT1
XINT1CR
7070h
Yes
(Level 1 or 6)
XINT2
XINT2CR
7071h
Yes
(Level 1 or 6)
NMI
—
—
No
PDPINT
EVIMRA
742Ch
Yes
(Level 1)
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