參數(shù)資料
型號(hào)： TMS320F241PGQ
元件分類： 數(shù)字信號(hào)處理
英文描述： 16-Bit Digital Signal Processor
中文描述： 16位數(shù)字信號(hào)處理器
文件頁(yè)數(shù)： 31/116頁(yè)
文件大小： 1485K
代理商： TMS320F241PGQ
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TMS320F243, TMS320F241
DSP CONTROLLERS
SPRS064B – DECEMBER 1997 – REVISED FEBRUARY 1999
31
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
interrupt request structure (continued)
Table 10.’F243/’F241 Interrupt Source Priority and Vectors (Continued)
INTERRUPT
NAME
OVERALL
PRIORITY
CPU
INTERRUPT
AND
VECTOR
ADDRESS
BIT
POSITION IN
PIRQRx AND
PIACKRx
PERIPHERAL
INTERRUPT
VECTOR
(PIV)
MASKABLE
SOURCE
PERIPHERAL
MODULE
DESCRIPTION
SPIINT
27
1.7
0005h
Y
SPI
SPI interrupt (low-priority)
RXINT
28
1.8
0006h
Y
SCI
SCI receiver interrupt
(low-priority mode)
TXINT
29
INT5
000Ah
1.9
0007h
Y
SCI
SCI transmitter interrupt
(low-priority mode)
CANMBINT
30
1.10
0040h
Y
CAN
CAN mailbox interrupt
(low-priority mode)
CANERINT
31
1.11
0041h
Y
CAN
CAN error interrupt
(low-priority mode)
ADCINT
32
1.12
0004h
Y
ADC
ADC interrupt
(low-priority)
XINT1
33
INT6
000Ch
1.13
0001h
Y
External
Interrupt Logic
External interrupt pins
(low-priority mode)
XINT2
34
1.14
0011h
Y
External
Interrupt Logic
External interrupt pins
(low-priority mode)
Reserved
000Eh
N/A
Y
CPU
Analysis interrupt
TRAP
N/A
0022h
N/A
N/A
CPU
TRAP instruction
Phantom
Interrupt
Vector
N/A
N/A
0000h
N/A
CPU
Phantom interrupt vector
interrupt acknowledge
When the CPU asserts its interrupt acknowledge, it simultaneously puts a value on the memory interface
program address bus, which corresponds to the CPU interrupt being acknowledged (it does this because it is
fetching the CPU interrupt vector from program memory, each INT has a vector stored in a dedicated program
memory address). This value is shown in Table 10, column 3, CPU Interrupt and Vector Address. The PIE
controller uses the CPU interrupt acknowledge to generate its internal signals to clear the current interrupt
requests.
interrupt vectors
When the CPU receives an interrupt request (INT), it does not know which peripheral event caused the request
(PIRQ). To enable the CPU to distinguish between all of these events, a unique interrupt vector is generated
in response to an active interrupt request getting acknowledged. This vector PIV is loaded into the Peripheral
Interrupt Vector Register (PIVR) in the PIE controller and can then be read by the CPU to generate a branch
to the respective Interrupt Service Routine (ISR).
In effect, there are two vector tables: a CPU vector table and a user-specified peripheral vector table. The CPU’s
vector table, which starts at 0000h, is used to get to the General Interrupt Service Routine (GISR) in response
to a CPU interrupt request (INT). A user-specified peripheral vector table is employed to get to the
Event-Specific Interrupt Service Routine (SISR), corresponding to the event which caused the peripheral
interrupt request (PIRQ). The code in the GISR should read the Peripheral Interrupt Vector Register (PIVR) after
saving any necessary context, and use this value PIV to generate a branch to the SISR.
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