![](http://datasheet.mmic.net.cn/370000/TMS320DM6443-07_datasheet_16739655/TMS320DM6443-07_8.png)
www.ti.com
TMS320DM6443
Digital Media System-on-Chip
SPRS282E–DECEMBER 2005–REVISED MARCH 2007
TMS320DM6443 Revision History (continued)
SEE
ADDITIONS/MODIFICATIONS/DELETIONS
Section 4
Section 5.3
Added new section,
System Interconnect
Added Footnotes (5) and (6) to Electrical Characteristics Over Recommended Ranges of Supply Voltage
and Operating Case Temperature
DM6443 Power and Clock Domains:
Added row for HPI to
Table 6-3
, DM6443 Power and Clock Domains
Added HPI box to
Figure 6-6
, PLL1 and PLL2 Clock Domain Block Diagram
Power and Sleep Controller (PSC) Module:
Added HPI to
Table 6-5
, DM6443 LPSC Assignments
Added HPI registers to
Table 6-6
, PSC Register Memory Map
Reset Electrical Data/Timing:
Updated Parameter 1 Description in
Table 6-8
, Timing Requirements for Reset
Updated Parameter 26 Description and MAX value in
Table 6-9
, Switching Characteristics Over
Recommended Operating Conditions During Reset
Changed section title to
External Clock Input From MXI/CLKIN Pin
Updated entire section
Clock PLLs:
Added new
Section 6.6.1
,
PLL1 and PLL2
ARM CPU Interrupts:
Added Interrupt 23, HPINT, to
Table 6-20
, DM6443 ARM Interrupts
DSP Interrupts:
Deleted AEGMUX0 and AEGMUX1 registers and replaced with Reserved in
Table 6-23
, C64x+ Interrupt
Controller Registers
Enhanced Direct Memory Access (EDMA) Controller:
Added paragraph
EDMA Peripheral Register Descriptions:
Updated Global Registers Hex Addresses for Reserved registers
(0x01c0 0264 -
0x01c0 028
3
and
0x01c0 028
8
- 0x01c0 02FF)
NAND (NAND, SmartMedia, xD):
Changed CS0 to CS
2
in the last bulleted item
EMIFA Electrical Data/Timing :
Updated
Table 6-35
, Switching Characteristics Over Recommended Operating Conditions for
Asynchronous Memory Cycles for EMIFA Module
Updated
Figure 6-21
, Asynchronous Memory Read Timing for EMIF
Updated
Figure 6-22
, Asynchronous Memory Write Timing for EMIF
Video Processing Sub-System (VPSS) Overview:
Added paragraph and equations after
Table 6-46
VPBE Electrical Data/Timing:
Updated Parameters 18 and 19 and added Footnote (3) in
Table 6-56
, Switching Characteristics Over
Recommended Operating Conditions for VPBE Control and Data Output With Respect to VCLK
Added new section,
Host Port Interface (HPI)
DAC Electrical/Data Timing:
Updated
Figure 6-51
, Typical Output Circuit for NTSC/PAL Video From DACs
UART Electrical Data/Timing:
Updated Parameters 4 and 5 MIN values in
Table 6-69
, Timing Requirements for UARTx Receive
SPI Master Mode Timings (Clock Phase = 0):
Updated Parameters 10 and 11 MIN values in
Table 6-74
, Switching Characteristics Over Recommended
Operating Conditions for SPI Master Mode [Clock Phase = 0]
SPI Master Mode Timings (Clock Phase = 1):
Updated Parameters 19 and 20 MIN values in
Table 6-76
, Switching Characteristics Over Recommended
Operating Conditions for SPI Master Mode [Clock Phase = 1]
Inter-Integrated Circuit (I2C):
Added Caution
I2C Electrical Data/Timing:
Updated
Table 6-79
, Switching Characteristics for I2C Timings
Updated
Figure 6-62
, I2C Transmit Timings
Added Caution
Section 6.3.1.3
Section 6.3.1.4
Section 6.4.1
Section 6.5
Section 6.6
Section 6.7.1
Section 6.7.2
Section 6.9
Section 6.9.2
Section 6.10.1.1
Section 6.10.1.2
Section 6.13
Section 6.13.2.3
Section 6.14
Section 6.13.2.4
Section 6.16.2
Section 6.17.2.1
Section 6.17.2.2
Section 6.18
Section 6.18.2
8
Revision History
Submit Documentation Feedback