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參數(shù)資料
| 型號(hào)： | TMPR3927F |
| 廠商： | Toshiba Corporation |
| 英文描述： | 32 Bit TX39 Family System RISC Microprocessor(32位TX39系列精簡指令集系統(tǒng)計(jì)算機(jī)微處理器) |
| 中文描述： | 32位TX39家庭系統(tǒng)RISC微處理器（32位TX39系列精簡指令集系統(tǒng)計(jì)算機(jī)微處理器） |
| 文件頁數(shù)： | 9/22頁 |
| 文件大小： | 272K |
| 代理商： | TMPR3927F |
TAEC_rev4_11-Jan-2000 9/22
TMPR3927F
TENTATIVE
ACE*
O
ROM Address Clock Enable
Enables capture of upper ten bits (multiplexed address) in an external latch. Used with
ROM, SRAM, and peripheral I/O. (Only active if next upper address differs from the
prior value.)
SWE*
O
Static RAM Write Enable
(Used in conjunction with ROM Controller)
ADDR[19:2]
O
Addresses for all memory devices
(During RESET*, the state of these pins are used to set the configuration of the TX3927.
Pin states are propagated through a transparent latch and are captured on the rising
edge of RESET*.)
Signal is connected to internal pull-up resistor.
OE*
O
Output Enable
Output enable for all devices controlled by the ROM Controller and for SMROM and
DIMM Flash.
CE*[7:0]
O
ROM Chip Enable
Chip selects to ROM, SRAM, FLASH and peripheral devices. Shared with SDRAM
SDCS*[7:2] via software assignment. Signals connected to internal pull-up resistors.
Data Byte Write Enable
BWE*[3:0]
O
Can be Byte write enables or Byte enables during a ROMC cycle.
DSF
O
Define Special Function
Multiplexed with PIO[1] and used for SGRAM special register functions.
PCI Interface
PCIAD[31..0]
I/O
The 32 Bit Address and Data Buses are multiplexed on the same PCI pins.
C_BE[3..0]
I/O
Command and Byte Enable
PAR
I/O
Parity for PCIAD[31..0] and C_BE[3..0]. Even Parity
FRAME*
I/O
Indicates beginning and duration of an transaction.
TRDY*
I/O
Target ready
IRDY*
I/O
Initiator ready
STOP*
I/O
STOP* indicates that the current Target is requesting Initiator to stop the current
transaction.
DEVSEL*
I/O
Device select
Indicates that an active device has decoded its address as the target of the current
access.
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