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參數(shù)資料
| 型號： | TMPR3927F |
| 廠商： | Toshiba Corporation |
| 英文描述： | 32 Bit TX39 Family System RISC Microprocessor(32位TX39系列精簡指令集系統(tǒng)計算機微處理器) |
| 中文描述： | 32位TX39家庭系統(tǒng)RISC微處理器（32位TX39系列精簡指令集系統(tǒng)計算機微處理器） |
| 文件頁數(shù)： | 12/22頁 |
| 文件大?。?/td> | 272K |
| 代理商： | TMPR3927F |
TAEC_rev4_11-Jan-2000 12/22
TMPR3927F
TENTATIVE
GPCST[3:0]
O
PC Trace Status
Outputs PC trace status information and serial monitor bus mode.
GDRESET*
I
Debug Reset
A reset input for the real-time debugging system. When this signal is asserted, the
debug support unit (DSU) is initialized.
Signal is connected to internal pull-up resistor.
GDBGE*
I
Debugger Enable
Indicates whether a real-time debugging system is connected external to the
TX39/H2 core. This signal must be low when a real-time debugging system is
connected or high when not connected. When DBGE* = high, the clock supplied to
the DSU block is stopped.
Signal is connected to internal pull-up resistor.
GSDI*
I
Serial Data Input/ Debug Interrupt
This signal functions as serial data/address input when operating with the serial
monitor bus interface or as target PC input when operating with the PC trace
interface.
Signal is connected to internal pull-up resistor.
Others
TEST*
I
Test Pin
This signal is used as internal functional test. It should be set to high.
Signal is connected to internal pull-up resistor.
SCAN_ENB*
I
Scan Mode Test Control
This signal is used as internal functional test. It should be set to high.
Signal is connected to internal pull-up resistor.
Power pins and Total pin count
PLL_VSS,
PLL_VDD
I
Power and Ground pins to internal PLL circuit.
VDD2
I
Power pins at 2.5V
VDDS
I
Power pins at 3.3V
VSS2,VSS
I
Ground pins
Pins: 240 pins
Total Pin Count
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