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參數(shù)資料
| 型號： | TMPR3927F |
| 廠商： | Toshiba Corporation |
| 英文描述： | 32 Bit TX39 Family System RISC Microprocessor(32位TX39系列精簡指令集系統(tǒng)計算機微處理器) |
| 中文描述： | 32位TX39家庭系統(tǒng)RISC微處理器（32位TX39系列精簡指令集系統(tǒng)計算機微處理器） |
| 文件頁數(shù)： | 8/22頁 |
| 文件大?。?/td> | 272K |
| 代理商： | TMPR3927F |
TAEC_rev4_11-Jan-2000 8/22
TMPR3927F
TENTATIVE
Interrupt Signals
NMI*
I
Non Maskable Interrupt
Non-Maskable interrupt input. Signal is connected to internal pull-up resistor.
INT[5:4]
I
INT [5:4] multiplexed with CTS0/RTS0
INT[3:0]
I
Interrupt Requests
Signal is connected to internal pull-up resistor.
Timer Interface
TIMER[1:0]
O
Timer Pulse Width Output
Multiplexed with other functions.
DMAREQ[3]/PIO15/TIMER[1]
DMAACK[3]/PIO14/TIMER[0]
DMADONE/PIO7/TIMER[0]
Memory Interface
SDCLK[4:0]
O
SDRAM Controller Clock
Signal is connected to internal pull-up resistor.
RAS*
O
Row Address Strobe
RAS* signal for the access of all synchronous memory devices.
CAS*
O
Column Address Strobe
CAS* signal for the access of all synchronous memory devices.
SDCS*[7:0]
O
Synchronous Memory Device Chip Select
Chip select for synchronous memory devices and 100-pin DIMM Flash.
SDCS[7:2] are shared with ROMCE[7:2] and are assigned by software. SDCS[7:6] are
also shared with DMA REQ/ACK[1] and PIO[11:10] via software assignment.
DQM[3:0]
O
Data Mask
During a write cycle, the DQM signal functions as a Data Mask and can control every
byte of the input data for SDRAMs. During a read cycle, the DQM functions as the
control of the SDRAM output buffers. The DQMs also function as byte write enables to
DIMM Flash during a write cycle.
WE*
O
Write Enable
Write enable signal for access of synchronous memory devices.
CKE
O
Clock Enable
Used for synchronous memory devices.
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