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7.3.4
Voltage detection flag and voltage detection status flag
The magnitude relation between the supply voltage (VDD) and the detection voltage (VDxLVL) can be
checked by reading VDCR1<VDxF> and VDCR1<VDxSF>.
If VDCR2<VDxEN> is set at "1", when the supply voltage (VDD) becomes lower than the detection voltage
(VDxLVL), VDCR1<VDxF> is set to "1" and is held in this state. VDCR1<VDxF> is not cleared to "0" when
the supply voltage (VDD) becomes equal to or higher than the detection voltage (VDxLVL).
When VDCR2<VDxEN> is cleared to "0" after VDCR1<VDxF> is set to "1", the previous state is still held.
To clear VDCR1<VDxF>, "0" must be written to it.
If VDCR2<VDxEN> is set at "1", when the supply voltage (VDD) becomes lower than the detection voltage
(VDxLVL), VDCR1<VDxSF> is set to "1". When the supply voltage (VDD) becomes equal to or higher than
the detection voltage (VDxLVL), VDCR1<VDxSF> is cleared to "0".
Unlike VDCR1<VDxF>, VDCR1<VDxSF> does not hold the set state.
Note 1: When the supply voltage (VDD) becomes lower than the detection voltage (VDxLVL) in the STOP, IDLE0 or
SLEEP0 mode, the voltage detection flag and the voltage detection status flag are changed after the oper-
ation mode is returned to NORMAL or SLOW mode.
Note 2: Depending on the voltage detection timing, the voltage detection status flag (VDxSF) may be changed earlier
than the voltage detection flag (VDxF) by a maximum of 2/fcgck[s].
Detection voltage level
VDD level
VDCR1<VDxF>
VDCR2<VDxEN>
Write 0 to VDCR1<VDxF>
The flag is not set because VDCR2<VDxEN> is 0 .
VDCR1<VDxSF>
Figure 7-3 Changes in the Voltage Detection Flag and the Voltage Detection Status Flag
7.3.5
Selecting the STOP mode release signal
By setting VDCR2<SRSS> to select the voltage detection STOP mode release signal as the STOP mode release
signal, STOP mode can be released when the supply voltage (VDD) becomes equal to or higher than the detection
voltage (VDxLVL).
To use this function, set VDCR2<VDxMOD> to "0" and set the operation mode to generate voltage detection
interrupt request signals. In addition, before the operation is switched to STOP mode, clear SYSCR1 <RELM>
to "0" and select the edge release mode.
If the level release mode is selected and the supply voltage (VDD) is equal to or higher than the detection
voltage (VDxLVL), STOP mode cannot be activated.
Setting VDCR2<SRSS> to "00" allows STOP mode to be released depending on the state of the STOP pin.
TMP89FH46L
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RA003