
T00PWM
Timer start
Additional
pulse
(Duty pulse
width)
128 counts
(cycle width)
128 counts
(cycle width)
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 5
Cycle 6
PWM0 pin output
(TFF0=“1”)
T00PWM
(Duty pulse
width)
Additional
pulse
Additional
pulse
PWM0 pin output
(TFF0=“0”)
INTTC00 interrupt
request
Figure 14-5 PWM0 Pulse Output
Set the initial state of the PWM0 pin at T00MOD<TFF0>. Setting T00MOD<TFF0> to "0" selects the "L"
level as the initial state of the PWM0 pin. Setting T00MOD<TFF0> to "1" selects the "H" level as the initial
state of the PWM0 pin. If the PWM0 pin is set as the function output pin in the port setting while the timer
is stopped, the value of T00MOD<TFF0> is output to the PWM0 pin.
Table 14-6 shows the list of output
levels of the PWM0 pin.
Table 14-6 List of Output Levels of PWM0 Pin
TFF0
PWM0 pin output level
Before the start of
operation
(initial state)
T00PWM
<PWMDUTY>
matched
(after the addition-
al pulse)
Overflow
Operation stop-
ped
(initial state)
0
L
H
L
1
H
L
H
And by setting "1" to T001CR<OUTAND> bit, a logical product (AND) pulse of TC00 and TC01’s output
can be output to PWM0 pin. By using this function, the remote-control waveform can be created eaily.
14.4.3.2
Operations
Setting T001CR<T00RUN> to "1" allows the up counter to increment based on the selected source clock.
When a match between the lower 7 bits of the up counter value and the value set to T00PWM<PWMDUTY>
is detected, the output of the PWM0 pin is reversed. When T00MOD<TFF0> is "0", the PWM0 pin changes
from the "L" to "H" level. When T00MOD<TFF0> is "1", the PWM0 pin changes from the "H" to "L" level.
If T00PWM<PWMAD> is "1", an additional pulse that corresponds to 1 count of the source clock is added
at the 2 × n-th match detection (n=1, 2, 3...). In other words, the PWM0 pin output is reversed at the timing
of T00PWM<PWMDUTY>+1. When T00MOD<TFF0> is "0", the period of the "L" level becomes longer
than the value set to T00<PWMDUTY> by 1 source clock. When T00MOD<TFF0> is "1", the period of the
"H" level becomes longer than the value set to T00PWM<PWMDUTY> by 1 source clock. This function
allows two cycles of output pulses to be handled with a resolution nearly equivalent to 8 bits.
No additional pulse is inserted when T00PWM<PWMAD> is "0".
Subsequently, the up counter continues counting up. When the up counter value reaches 128, an overflow
occurs and the up counter is cleared to "0x00". At the same time, the output of the PWM0 pin is reversed.
When T00MOD<TFF0> is "0", the PWM0 pin changes from the "H" to "L" level. When T00MOD<TFF0>
TMP89FH46L
Page 191
RA004