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2.2.1.1
RAM
The RAM is mapped in the data area immediately after reset release.
By setting SYSCR3<RAREA> to "1" and writing 0xD4 to SYSCR4, RAM can be mapped to 0x0040to
0x083F in the code area to execute the program.
At this time, by setting SYSCR<RVCTR> to "1" and writing 0xD4 to SYSCR4, vector table for vector call
instructions and interrupt except reset can be mapped to RAM.
In the serial PROM mode, the RAM is mapped to 0x0040 to 0x083F in the code area, regardless of the
value of SYSCR3<RAREA>. The program can be executed on the RAM using the RAM loader function.
Note 1: When the RAM is not mapped in the code area, the SWI instruction is fetched from 0x0040 to 0x083F.
Note2: The contents of the RAM become unstable when the power is turned on and immediately after a reset
is released. To execute the program by using the RAM, transfer the program to be executed in the
initialization routine.
System control register 3
SYSCR3
(0x0FDE)
7
6
5
4
3
2
1
0
Bit Symbol
-
RVCTR
RAREA
(RSTDIS)
Read/Write
R
R/W
After reset
0
RAREA
Specifies mapping of the RAM in
the code area
0 : The RAM is not mapped from 0x0040 to 0x083F in the code area.
1 : The RAM is mapped from 0x0040 to 0x083F in the code area.
RVCTR
Specifies mapping of the vector ta-
ble for vector call instructions and
interrupts
Vector table for vector call instruc-
tions
Vector table for interrupt
0 : 0xFFA0 to 0xFFBF in the code area 0xFFCC to 0xFFFF in the code area
1 : 0x01A0 to 0x01BF in the code area 0x01CC to 0x01FD in the code area
Note 1: The value of SYSCR3<RAREA> is invalid until 0xD4 is written into SYSCR4.
Note 2: To assign vector address areas to RAM, set SYSCR3<RVCTR> to "1" and SYSCR3<RAREA> to "1".
Note 3: Do not set SYSCR3<RVCTR> to "0" by using the RAM loader program. If an interrupt occurs with SYSCR3<RVCTR> set
to "0", the BOOTROM area is referenced as a vector address and, therefore, the program will not function properly.
Note 4: Bits 7 to 3 of SYSCR3 are read as "0".
System control register 4
SYSCR4
(0x0FDF)
7
6
5
4
3
2
1
0
Bit Symbol
SYSCR4
Read/Write
W
After reset
0
SYSCR4
Writes the SYSCR3 data control
code.
0xB2 :
0xD4 :
0x71 :
Enables the contents of SYSCR3<RSTDIS>.
Enables the contents of SYSCR3<RAREA> and SYSCR3 <RVCTR>.
Enables the contents of IRSTSR<FCLR>
Others : Invalid
Note 1: SYSCR4 is a write-only register, and must not be accessed by using a read-modify-write instruction, such as a bit oper-
ation.
Note 2: After SYSCR3<RSTDIS> is modified, SYSCR4 should be written 0xB2 (Enable code for SYSCR3<RSTDIS>) in NORMAL
mode when fcgck is fc/4 (CGCR<FCGCKSEL>=00). Otherwise, SYSCR3<RSTDIS> may be enabled at unexpected tim-
ing.
Note 3: After IRSTSR<FCLR> is modified, SYSCR4 should be written 0x71 (Enable code for IRSTSR<FCLR> in NORMAL mode
when fcgck is fc/4 (CGCR<FCGCKSEL>=00). Otherwise, IRSTSR<FCLR> may be enabled at unexpected timing.
TMP89FH46L
2. CPU Core
2.2 Memory space
Page 10
RA004