參數(shù)資料
型號: TMP32C6411ZLZ
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號處理
英文描述: FIXED POINT DIGITAL SIGNAL PROCESSOR
中文描述: 定點數(shù)字信號處理器
文件頁數(shù): 78/119頁
文件大?。?/td> 1742K
代理商: TMP32C6411ZLZ
SPRS196H MARCH 2002 REVISED JULY 2004
78
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
PROGRAMMABLE SYNCHRONOUS INTERFACE TIMING
timing requirements for programmable synchronous interface cycles (see Figure 24)
NO.
300
UNIT
MIN
MAX
6
tsu(EDV-EKOxH)
th(EKOxH-EDV)
Setup time, read EDx valid before ECLKOUTx high
6.4
ns
7
Hold time, read EDx valid after ECLKOUTx high
1.5
ns
switching characteristics over recommended operating conditions for programmable
synchronous interface cycles
(see Figure 24Figure 26)
NO.
PARAMETER
300
UNIT
MIN
MAX
1
td(EKOxH-CEV)
td(EKOxH-BEV)
td(EKOxH-BEIV)
td(EKOxH-EAV)
td(EKOxH-EAIV)
td(EKOxH-ADSV)
td(EKOxH-OEV)
td(EKOxH-EDV)
td(EKOxH-EDIV)
td(EKOxH-WEV)
Delay time, ECLKOUTx high to CEx valid
1.3
9.7
ns
2
Delay time, ECLKOUTx high to BEx valid
9.7
ns
3
Delay time, ECLKOUTx high to BEx invalid
1.3
ns
4
Delay time, ECLKOUTx high to EAx valid
9.7
ns
5
Delay time, ECLKOUTx high to EAx invalid
1.3
ns
8
Delay time, ECLKOUTx high to SADS/SRE valid
1.3
9.7
ns
9
Delay time, ECLKOUTx high to, SOE valid
1.3
9.7
ns
10
Delay time, ECLKOUTx high to EDx valid
9.7
ns
11
Delay time, ECLKOUTx high to EDx invalid
1.3
ns
12
Delay time, ECLKOUTx high to SWE valid
1.3
9.7
ns
The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC):
Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency
Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency
CEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, CEx goes inactive after the final command has been issued
(CEEXT = 0). For synchronous FIFO interface with glue, CEx is active when SOE is active (CEEXT = 1).
Function of SADS/SRE (RENEN): For standard SBSRAM or ZBT SRAM interface, SADS/SRE acts as SADS with deselect cycles
(RENEN = 0). For FIFO interface, SADS/SRE acts as SRE with NO deselect cycles (RENEN = 1).
Synchronization clock (SNCCLK): Synchronized to ECLKOUT1 or ECLKOUT2
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