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| 型號(hào)： | TMP32C6411ZLZ |
| 廠商： | Texas Instruments, Inc. |
| 元件分類(lèi)： | 數(shù)字信號(hào)處理 |
| 英文描述： | FIXED POINT DIGITAL SIGNAL PROCESSOR |
| 中文描述： | 定點(diǎn)數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 108/119頁(yè) |
| 文件大?。?/td> | 1742K |
| 代理商： | TMP32C6411ZLZ |
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SPRS196H MARCH 2002 REVISED JULY 2004
108
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING (CONTINUED)
timing requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
(see Figure 54)
300
NO.
MASTER
MIN
SLAVE
MIN
UNIT
MAX
MAX
4
tsu(DRV-CKXH)
th(CKXH-DRV)
Setup time, DR valid before CLKX high
12
2 12P
ns
5
Hold time, DR valid after CLKX high
4
5 + 24P
ns
P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns.
For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics over recommended operating conditions for McBSP as SPI Master or
Slave: CLKSTP = 11b, CLKXP = 0
(see Figure 54)
300
NO.
PARAMETER
MASTER§
SLAVE
UNIT
MIN
MAX
MIN
MAX
1
th(CKXL-FXL)
td(FXL-CKXH)
td(CKXL-DXV)
Hold time, FSX low after CLKX low
Delay time, FSX low to CLKX high#
L 2
L + 3
ns
2
T 2
T + 3
ns
3
Delay time, CLKX low to DX valid
2
4
12P+4
20P+17
ns
6
tdis(CKXL-DXHZ)
Disable time, DX high impedance following last data bit from
CLKX low
2
4
12P+3
20P+17
ns
7
td(FXL-DXV)
Delay time, FSX low to DX valid
H 2
H + 4
8P+2
16P+17
ns
P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns.
For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
§S =
Sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency)
=
Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T =
CLKX period = (1 + CLKGDV) * S
H =
CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L =
CLKX low pulse width
= (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP
#FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock
(CLKX).
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
4
3
7
6
2
1
CLKX
FSX
DX
DR
5
Figure 54. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
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