參數(shù)資料
型號： TMP32C6411ZLZ
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： FIXED POINT DIGITAL SIGNAL PROCESSOR
中文描述： 定點數(shù)字信號處理器
文件頁數(shù)： 39/119頁
文件大?。?/td> 1742K
代理商： TMP32C6411ZLZ
SPRS196H MARCH 2002 REVISED JULY 2004
39
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
Terminal Functions (Continued)
SIGNAL
TYPE
IPD/
IPU
DESCRIPTION
NAME
NO.
RESETS, INTERRUPTS, AND GENERAL-PURPOSE INPUT/OUTPUTS (CONTINUED)
GP0
AF6
I/O/Z
IPD
GPIO 0 pin.
The general-purpose I/O 0 pin (GPIO 0) (
I/O/Z
) can be programmed as GPIO 0 (
input only
)
[default] or as GPIO 0 (
output only
) pin or output as a general-purpose interrupt (GP0INT)
signal (
output only
).
This pin has no function at default [default] or this pin can be programmed as a GPIO 8 pin
(
I/O/Z
).
GP8
AE4
I/O/Z
IPD
CLKOUT6/GP2§
AD6
I/O/Z
IPD
Clock output at 1/6 of the device speed (
O/Z
) [default] or this pin can be programmed as a
GPIO 2 pin (
I/O/Z
).
CLKOUT4/GP1§
AE6
I/O/Z
IPD
Clock output at 1/4 of the device speed (
O/Z
) [default] or this pin can be programmed as a
GPIO 1 pin (
I/O/Z
).
HOST-PORT INTERFACE (HPI) or PERIPHERAL COMPONENT INTERCONNECT (PCI)
HINT/
PFRAME§
R4
I/O/Z
Host interrupt from DSP to host (
O
) [default] or PCI frame (
I/O/Z
)
HCNTL1/
PDEVSEL§
R1
I/O/Z
Host control selects between control, address, or data registers (
I
) [default] or PCI device
select (
I/O/Z
).
HCNTL0/
PSTOP§
T4
I/O/Z
Host control selects between control, address, or data registers (
I
) [default] or PCI stop
(
I/O/Z
)
HHWIL/PTRDY§
R3
I/O/Z
Host half-word select first or second half-word (not necessarily high or low order)
[For HPI16 bus width selection only] (
I
) [default] or PCI target ready (
I/O/Z
)
HR/W/PCBE2§
HAS/PPAR§
HCS/PPERR§
HDS1/PSERR§
HDS2/PCBE1§
HRDY/PIRDY§
HD31/AD31§
HD30/AD30§
HD29/AD29§
HD28/AD28§
HD27/AD27§
HD26/AD26§
HD25/AD25§
HD24/AD24§
HD23/AD23§
HD22/AD22§
HD21/AD21§
HD20/AD20§
HD19/AD19§
HD18/AD18§
HD17/AD17§
HD16/AD16§
HD15/AD15§
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k
IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-k
resistor should be used, unless otherwise noted.)
§These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
P1
I/O/Z
Host read or write select (
I
) [default] or PCI command/byte enable 2 (
I/O/Z
)
T3
I/O/Z
Host address strobe (
I
) [default] or PCI parity (
I/O/Z
)
R2
I/O/Z
Host chip select (
I
) [default] or PCI parity error (
I/O/Z
)
T1
I/O/Z
Host data strobe 1 (
I
) [default] or PCI system error (
I/O/Z
)
T2
I/O/Z
Host data strobe 2 (
I
) [default] or PCI command/byte enable 1 (
I/O/Z
)
P4
I/O/Z
Host ready from DSP to host (
O
) [default] or PCI initiator ready (
I/O/Z
).
J2
K3
J1
Host-port data (
I/O/Z
) [default] or PCI data-address bus (
I/O/Z
)
K4
K2
As HPI data bus (PCI_EN pin = 0)
Used for transfer of data, address, and control
Host-Port bus width (HPI_WIDTH) user-configurable at device reset via a 10-k
resistor
pullup/pulldown resistor on the HD5 pin:
L3
K1
L4
HD5 pin = 0: HPI operates as an HPI16.
(HPI bus is 16 bits wide. HD[15:0] pins are used and the remaining HD[31:16] pins are
reserved pins in the high-impedance state.)
L1
I/O/Z
M4
M2
HD5 pin = 1: HPI operates as an HPI32.
(HPI bus is 32 bits wide. All HD[31:0] pins are used for host-port operations.)
N4
M1
N5
As PCI data-address bus (PCI_EN pin = 1)
Used for transfer of data and address
N1
P5
U4
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