- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄382648 > TMP320C6413GTS500 (Texas Instruments, Inc.) Fixed-Point Digital Signal Processors PDF資料下載
參數(shù)資料
| 型號(hào)： | TMP320C6413GTS500 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | Fixed-Point Digital Signal Processors |
| 中文描述： | 定點(diǎn)數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 56/140頁(yè) |
| 文件大?。?/td> | 1958K |
| 代理商： | TMP320C6413GTS500 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)當(dāng)前第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)
Terminal Functions
56
April 2004
Revised May 2005
SPRS247E
Table 3
9. Terminal Functions
SIGNAL
NAME
TYPE
IPD/
IPU
DESCRIPTION
NO.
CLOCK/PLL CONFIGURATION
Clock Input. This clock is the input to the on-chip PLL.
Clock output at 1/4 of the device speed (
O/Z
) [default] or this pin can be programmed as
a GP0 1 pin (
I/O/Z
).
CLKIN
A12
I
IPD
CLKOUT4/GP0[1]
§
A2
I/O/Z
IPU
CLKOUT6/GP0[2]
§
B3
I/O/Z
IPU
Clock output at 1/6 of the device speed (
O/Z
) [default] or this pin can be programmed as
a GP0 2 pin (
I/O/Z
).
CLKINSEL
A11
I
IPU
CLKIN select. Selects whether the PLL input clock is CLKIN [pin high] or directly from
the crystal oscillator (OSCIN and OSCOUT) [pin low].
For proper device operation, this pin
must
be used in conjunction with the OSC_DIS
pin.
CLKMODE3
CLKMODE2
CLKMODE1
CLKMODE0
PLLV
OSCIN
OSCOUT
C11
B10
A13
C13
C12
A6
A7
I
I
I
I
IPD
IPD
IPD
IPD
Clock mode selects
Selects whether the CPU clock frequency = input clock frequency x1 (Bypass), x5,
x6 x7 x8 x9 x10 x11 x12 x16 x18 x19 x20 x21 x22 or x24
x6, x7, x8, x9, x10, x11, x12, x16, x18, x19, x20, x21, x22, or x24.
For more details on the CLKMODE pins and the PLL multiply factors, see the Clock
PLL section of this data sheet.
PLL voltage supply
Crystal oscillator Input (XI)
Crystal oscillator output (XO)
Power for crystal oscillator (1.2 V),
Do not
connect to board power 1.4 V; for optimum
performance, connected internally. If CLKIN is used instead of the oscillator, then this
pin can be left open or connected to CV
DD
.
Ground for crystal oscillator,
Do not
connect to board ground; for optimum
performance, connected internally. If CLKIN is used instead of the oscillator, then this
pin can be left open or connected to V
SS
.
Oscillator disable select.
For proper device operation, this pin
must
follow the CLKINSEL pin operation.
0
OSC enabled; CLKINSEL
must
be 0
1
OSC disabled (default); CLKINSEL
must
be 1
JTAG EMULATION
JTAG test-port mode select
JTAG test-port data out
JTAG test-port data in
JTAG test-port clock
JTAG test-port reset. For IEEE 1149.1 JTAG compatibility, see the IEEE 1149.1 JTAG
compatibility statement portion of this data sheet.
Emulation pin 0
#
Emulation pin 1
#
A
I
O
—
—
OSCV
DD
B6
S
—
OSCV
SS
C6
GND
—
OSC_DIS
B7
I
IPU
TMS
TDO
TDI
TCK
U3
T4
T1
T2
I
IPU
IPU
IPU
IPU
O/Z
I
I
TRST
U1
I
IPD
EMU0
EMU1
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog Signal
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k
IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-k
resistor should be used.)
§
These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
PLLV is not part of external voltage supply. See the Clock PLL and Oscillator section for information on how to connect this pin.
#
The EMU0 and EMU1 pins are internally pulled up with 30-k
resistors; therefore, for emulation and normal operation, no external
pullup/pulldown resistors are necessary. However, for boundary scan operation, pull down the EMU1 and EMU0 pins with a dedicated 1-k
resistor.
R1
T3
I/O/Z
I/O/Z
IPU
IPU
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TMP320C6413ZTSA500 | Fixed-Point Digital Signal Processors |
| TMX320F2810GHHA | DIGITAL SIGNAL PROCESSORS |
| TMX320F2810PBKA | DIGITAL SIGNAL PROCESSORS |
| TMP320F2810PBKA | DIGITAL SIGNAL PROCESSORS |
| TMX320F2810PBKAEP | Digital Signal Processors |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TMP320C6413GTSA400 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Fixed-Point Digital Signal Processors |
| TMP320C6413GTSA500 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Fixed-Point Digital Signal Processors |
| TMP320C6413ZTS400 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Fixed-Point Digital Signal Processors |
| TMP320C6413ZTS500 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Fixed-Point Digital Signal Processors |
| TMP320C6413ZTSA400 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Fixed-Point Digital Signal Processors |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。