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| 型號(hào)： | TMP320C6413GTS500 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | Fixed-Point Digital Signal Processors |
| 中文描述： | 定點(diǎn)數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 50/140頁(yè) |
| 文件大?。?/td> | 1958K |
| 代理商： | TMP320C6413GTS500 |
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Device Configurations
50
April 2004
Revised May 2005
SPRS247E
3.5
Device Status Register Description
The device status register depicts the status of the device peripheral selection. Once set, these bits will remain
set until a device reset; therefore, these bits should be masked when reading the DEVSTAT register since their
values can change. For the actual register bit names and their associated bit field descriptions, see Figure 3
4
and Table 3
6.
31
24
Reserved
R-100x0111
23
19
18
17
16
PLLM
Reserved
OSC EXT RES
CLKINSEL
R-xxxxx
R-
1
R-x
R-x
15
14
13
12
11
10
9
8
Reserved
CLKMODE3
Reserved
HPI-WIDTH
Reserved
HPI_EN
R-000
R-x
R-0
R-x
R-0
R-x
7
6
5
4
3
2
1
0
CLKMODE2
CLKMODE1
CLKMODE0
LENDIAN
BOOTMODE1
BOOTMODE0
AECLKINSEL1
AECLKINSEL0
R-x
R-x
R-x
R-x
R-x
R-x
R-x
R-x
Legend:
R = Read only; R/W = Read/Write; -n = value after reset
Figure 3
4. Device Status Register (DEVSTAT) Description
0x01B3 F004
Table 3
6. Device Status (DEVSTAT) Register Selection Bit Descriptions
NAME
Reserved
Reserved. Read-only, writes have no effect.
PLL multiply factor status bits.
Shows the status of the PLL multiply mode selected; whether the CPU clock frequency equals the input
clock frequency x1 (Bypass), x5, x6, x7, x8, x9, x10, x11, x12, x16, x18, x19, x20, x21, x22, or x24.
For more detailed information on the PLL multiply factors, see the
Clock PLL and Oscillator
section of this
data sheet.
BIT
31:24
DESCRIPTION
23:19
PLLM
18
Reserved
Reserved. Read-only, writes have no effect.
Oscillator external resistor status bit.
Shows the status internal or external of the OSC bias resistor.
0
=
Normal functional mode with
interna
l bias resistor.
1
=
Normal functional mode with
external
bias resistor [default; internally tied high].
PLL input clock select status bit.
Shows the status of whether the PLL input clock is CLKIN [pin high] or directly from the crystal oscillator
(OSCIN and OSCOUT) [pin low]
0
=
Crystal oscillator (OSCIN and OSCOUT).
1
=
CLKIN (default).
17
OSC EXT RES
16
CLKINSEL
15:13
11
Reserved
Reserved
Reserved. Read-only, writes have no effect.
Reserved. Read-only, writes have no effect.
HPI bus width control bit.
Shows the status of whether the HPI bus operates in 32-bit mode or in 16-bit mode (default).
0
=
HPI operates in 16-bit mode. (default).
1
=
HPI operates in 32-bit mode.
Reserved. Read-only, writes have no effect.
HPI_EN pin status bit.
Shows the status at device reset of the HPI_EN pin, which controls the HPI peripheral as enabled [default]
or disabled.
0
=
HPI_EN pin is low, meaning the HPI peripheral is enabled (default).
1
=
HPI_EN pin is high, meaning the HPI peripheral is disabled.
10
HPI_WIDTH
9
Reserved
8
HPI_EN
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