• 參數(shù)資料
    型號(hào): TMP320C6413GTS500
    廠商: Texas Instruments, Inc.
    元件分類: 數(shù)字信號(hào)處理
    英文描述: Fixed-Point Digital Signal Processors
    中文描述: 定點(diǎn)數(shù)字信號(hào)處理器
    文件頁(yè)數(shù): 125/140頁(yè)
    文件大?。?/td> 1958K
    代理商: TMP320C6413GTS500
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    Multichannel Buffered Serial Port (McBSP) Timing
    125
    April 2004
    Revised May 2005
    SPRS247E
    7.12
    Multichannel Buffered Serial Port (McBSP) Timing
    Table 7
    26. Timing Requirements for McBSP
    (see Figure 7
    36)
    NO.
    400
    500
    UNIT
    MIN
    MAX
    2
    3
    t
    c(CKRX)
    t
    w(CKRX)
    Cycle time, CLKR/X
    Pulse duration, CLKR/X high or CLKR/X low
    CLKR/X ext
    CLKR/X ext
    CLKR int
    CLKR ext
    CLKR int
    CLKR ext
    CLKR int
    CLKR ext
    CLKR int
    CLKR ext
    CLKX int
    CLKX ext
    CLKX int
    CLKX ext
    4P or 6.67
    §
    0.5t
    c(CKRX)
    1
    9
    1.3
    6
    3
    8
    0.9
    3
    3.1
    9
    1.3
    6
    3
    ns
    ns
    5
    t
    su(FRH-CKRL)
    Setup time external FSR high before CLKR low
    Setup time, external FSR high before CLKR low
    ns
    6
    t
    h(CKRL-FRH)
    Hold time external FSR high after CLKR low
    Hold time, external FSR high after CLKR low
    ns
    7
    t
    su(DRV-CKRL)
    Setup time DR valid before CLKR low
    Setup time, DR valid before CLKR low
    ns
    8
    t
    h(CKRL-DRV)
    Hold time DR valid after CLKR low
    Hold time, DR valid after CLKR low
    ns
    10
    t
    su(FXH-CKXL)
    Setup time external FSX high before CLKX low
    Setup time, external FSX high before CLKX low
    ns
    11
    t
    h(CKXL-FXH)
    Hold time external FSX high after CLKX low
    Hold time, external FSX high after CLKX low
    ns
    CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
    P = 1/CPU clock frequency in ns. For example, when running parts at 500 MHz, use P = 2 ns.
    §
    Use whichever value is greater. Minimum CLKR/X cycle times
    must
    be met, even when CLKR/X is generated by an internal clock source. The
    minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing
    requirements.
    This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.
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    相關(guān)代理商/技術(shù)參數(shù)
    參數(shù)描述
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