參數(shù)資料
型號： TMC2491AR2C
廠商： FAIRCHILD SEMICONDUCTOR CORP
元件分類： 顏色信號轉(zhuǎn)換
英文描述： COLOR SIGNAL ENCODER, PQCC44
封裝： PLASTIC, LCC-44
文件頁數(shù)： 25/36頁
文件大?。?/td> 208K
代理商： TMC2491AR2C
PRODUCT SPECIFICATION
TMC2490A/TMC2491A
31
Applications Information
The circuit in Figure 24 shows the connection of power sup-
ply voltages, output reconstruction lters and the external
voltage reference. All VDD pins should be connected to the
same power source.
The full-scale output voltage level, VOUT, on the COMPOS-
ITE, LUMA, and CHROMA pins is found from:
VOUT
= IOUT x RL = K x IREF x RL
= K x (VREF/RREF) x RL
where:
IOUT is the full-scale output current sourced by the
TMC2490(1)A D/A converters.
RL is the net resistive load on the COMPOSITE,
CHROMA, and LUMA output pins.
K is a constant for the TMC2490(1)A D/A converters
(approximately equal to 10.4).
IREF is the reference current owing out of the RREF pin
to ground.
VREF is the voltage measured on the VREF pin.
RREF is the total resistance connected between the RREF
pin and ground.
A 0.1
F capacitor should be connected between the CBYP
pin and the adjacent VDDA, pin.
The reference voltage in Figure 24 is from an LM185 1.2
Volt band-gap reference. The 392 Ohm resistor connected
from RREF to ground sets the overall "gain" of the three D/A
converters of the TMC2490(1)A. A 787
resistor is used for
single 75
termination. Varying RREF ±5% will cause the
full-scale output voltage on COMPOSITE, LUMA, and
CHROMA to vary by
±5%.
The suggested output reconstruction lter is the same one
used on the TMC2063P7C Demonstration Board. The phase
and frequency response of this lter is shown in Figure 23.
The Schottky diode is for ESD protection.
Figure 23. Response of Recommended Output Filter
-40
-50
-60
-30
-20
-10
0
-120
-160
-200
-80
-40
0
40
0
5
10
15
20
25
Frequency (MHz)
Analog Reconstruction Filter
Attenuation
(dB)
Phase
(deg)
24365A
Figure 24. Typical Application Circuit
+5V
TMC2490A
TMC2491A
Multistandard
Digital Video
Encoder
MPEG-2
Decoder
VDD
GND
PXCK
CHROMA
VIDEO
FROM
ENCODER
VIDEO
OUTPUT
TO 75
LOAD
75
1.0
H
1.8
H
27pF
330pF
1N5818
75
100pF
65-2490(1)A-03
VSYNC
HSYNC
PD7-0
PIXCLK
B/
T
HSYNC
YC7-0
PDC
SELC
10
F
LPF
27.0 MHz
CLOCK
CONTROL INTERFACE
VIDEO
INTERFACE
0.1
F
0.1
F
0.1
F
392
3.3k
LM185-1.2
SER
RESET
SA1
SA0/ADR
D
7-0
SCL/
CS
SDA
/
R/
W
LUMA
COMPOSITE
CBYP
VREF
VDDA
RREF
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