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參數(shù)資料
| 型號： | TMC2491AR2C |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 顏色信號轉換 |
| 英文描述： | COLOR SIGNAL ENCODER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 2/36頁 |
| 文件大?。?/td> | 208K |
| 代理商： | TMC2491AR2C |
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PRODUCT SPECIFICATION
TMC2490A/TMC2491A
10
Control Register Denitions (continued)
Closed-Caption Insertion (20)
7
6
5
4
3
2
1
0
CCD1
Reg
Bit
Name
Description
20
7–0
CCD1
First Byte of CC Data. Bit 0 is the LSB. The MSB will be overwritten by an
ODD Parity bit if CCPAR is HIGH.
Closed-Caption Insertion (21)
7
6
5
4
3
2
1
0
CCD2
Reg
Bit
Name
Description
21
7–0
CCD2
Second Byte of CC Data. Bit 0 is the LSB. The MSB will be overwritten by
an ODD Parity bit if CCPAR is HIGH.
Closed-Caption Insertion (22)
7
6
5
4
3
2
1
0
CCON
CCRTS
CCPAR
CCFLD
CCLINE
Reg
Bit
Name
Description
22
7
CCON
Enable CC Data Packet. Command the CC data generator to send either
CC data or a NULL byte whenever the specified line is transmitted.
22
6
CCRTS
Request To Send Data. This bit is set HIGH by the user when bytes 20 and
21 have been loaded with the next two bytes to be sent. When the encoder
reaches the falling edge of the HSYNC preceding the line specified in bits
4-0 of this register, data will be transferred from registers 20 and 21, and
RTS will be reset LOW. A new pair of bytes may then be loaded into
registers 20 and 21. If CCON = 1 and CCRTS = 0 when the CC line is to be
sent, NULL bytes will be sent.
22
5
CCPAR
Auto Parity Generation. When set HIGH, the encoder replaces the MSB of
bytes 20 and 21 with a calculated ODD parity. When set LOW, the CC
processor transmits the 16 bits exactly as loaded into registers 20 and 21.
22
4
CCFLD
CC Field Select. When LOW, CC data is transmitted on the selected line of
ODD fields. When HIGH, it is sent on EVEN fields.
22
3–0
CCLINE
CC Line Select. Defines (with an offset) the line on which CC data is
transmitted.
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