參數(shù)資料
型號(hào)： TMC2360
廠商： Fairchild Semiconductor Corporation
英文描述： VGA to NTSC/PAL Video Output Processor(VGA 到NTSC/PAL 視頻輸出處理器)
中文描述： VGA轉(zhuǎn)NTSC / PAL視頻輸出處理器（顯卡到的NTSC / PAL視頻輸出處理器）
文件頁(yè)數(shù)： 7/24頁(yè)
文件大?。?/td> 230K
代理商： TMC2360
PRODUCT SPECIFICATION
TMC2360
7
Clocks
There are three internal clocks, ADCLK, PXCK, and
27MHz. ADCLK is the clock for the A/D converters with
sampling on the edge selected by PHASE. PXCK is the
encoder clock for sequencing data to the D/A converters at a
2X rate. 27MHz is the reference clock from which the
chroma subcarrier data is synthesized.
ADCLK and PXCK clocks may be derived from internal or
external phase-locked loops. Only an external controller con-
taining the phase detector, charge pump, and VCO is needed
for each loop. An internal divider programmed with the cor-
rect counts is included within the TMC2360.
Control of the internal/external PLL modes is either via the
A
0
and A
1
pins (see Table 1) or through the VGA1 Control
register, which can be programmed via the microprocessor
port.
With control via A
0
and A
1
pins, the outputs PDIVM and
ADIVN are high impedance unless either PLL is pro-
grammed to be external. A
0
and A
1
also control the direction
of the ADCLK and PXCK clock pins. Each clock (ADCLK
and PXCK) is an output in the internal mode and an output
in the external mode.
Table 1. Internal/External Phase-locked Loop Selection (MPEN = L)
A
1
0
0
1
1
A
0
0
1
0
1
PLLA
Internal
Internal
External
External
PLLP
Internal
External
Internal
External
ADIVN
High-Z
1/N
1/N
1/N
PDIVM
High-Z
1/M
1/M
1/M
ADCLK
Output
Output
Input
Input
PXCK
Output
Input
Output
Input
A/D Clock (ADCLK)
ADCLK is the buffered analog-to-digital converter clock
output which is derived from incoming VGA horizontal sync
(VGAHS) by a phase-lock loop (PLL). Either an internal
PLL or an external PLL controller may be selected by pro-
gramming pin A
1
.
A/D Clock frequency is set by the PLL divide-by-N counter
where N is the number of A/D samples between the horizon-
tal sync pulses in each VGA line.
Pre-programmed values selected by the TVSTD
1-0
and
PAL800 control inputs set N and the clock frequency as
shown in Table 2.
Table 2. VGA A/D Clock
For an internal loop, the recommended loop filter to be con-
nected to the LPF
A
pin is shown in Figure 1.
Figure 1. PLL Low Pass Filter
Pixel Clock (PXCK)
PXCK is the buffered video encoder clock output which is
derived from the incoming VGA HSYNC signal by a second
phase-lock loop. Either an internal PLL or an external PLL
controller may be selected by programming pin A
0
.
With the internal loop selected, Figure 1 shows the recom-
mended loop filter, which should be connected to LPF
P.
Clock frequency is set by the PLL divide-by-M counter. M is
the number of encoder samples between horizontal sync
pulses. Because of 2X oversampling, the pixel rate is twice
the TV square pixel rate. Table 3 shows the video output
clock rates and M values.
Television
Standard
NTSC
PAL640
PAL800
PALM
TVSTD
1-0
PAL800
0x
10
10
11
ADCLK
Freq. (MHz)
25.175
25.250
36.000
25.175
N
0
0
1
0
800
808
1152
800
LPF
0.1
μ
F
680pF
29001A
39K
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