參數(shù)資料
型號(hào)： TMC2360
廠商： Fairchild Semiconductor Corporation
英文描述： VGA to NTSC/PAL Video Output Processor(VGA 到NTSC/PAL 視頻輸出處理器)
中文描述： VGA轉(zhuǎn)NTSC / PAL視頻輸出處理器（顯卡到的NTSC / PAL視頻輸出處理器）
文件頁數(shù)： 6/24頁
文件大?。?/td> 230K
代理商： TMC2360
TMC2360
PRODUCT SPECIFICATION
6
Notes:
CMOS
P
= CMOS with light pull-up
CMOS
S
= CMOS with Schmitt Trigger
Microprocessor Interface
MPEN
30
TTL
Microprocessor Port Enable.
With MPEN = LOW, the port is
disabled and control is via individual pins. With MPEN = HIGH,
selected functions may be accessed through the microprocessor
port.
External PXCK Phase-locked Loop Select/Address Bit.
Dual
function pin. If MPEN = HIGH, A
0
is the microprocessor port address
bit A0. If MPEN = LOW, A
0
configures the PXCK PLL inputs and
outputs.
External ADCLK Phase-locked Loop Select.
If
MPEN = LOW, A1 configures the ADCLK PLL inputs and outputs.
Read/Write.
Read/Write selects the direction of the 8-bit data bus.
Chip Enable.
When CE = H, D
7-0
are high impedance. When CE = L,
R/W sets D
7-0
to either the read or write state.
Data bits.
Data bus is high impedance unless CE = L and R/W = H.
A
0
32
TTL
A
1
31
TTL
R/W
CE
33
34
TTL
TTL
D
7-0
18, 19, 20, 21,
22, 23, 24, 25
TTL
Power and Ground
V
DD
7, 9, 14, 29,
35, 62,
51, 52, 60, 75,
76
65
+5.0 V
Digital Power Supply.
Supplies +5V power to internal digital circuits.
V
DDA
+5.0 V
Analog Power Supply.
Supples +5V power to internal analog
circuits. V
DD
and V
DDA
must originate from the same source.
A/D Phase Locked Loop +5V Power.
V
DDPLLA
and V
DD
must
originate from the same source.
Encoder Phase Locked Loop +5V Power.
V
DDPLLP
and V
DD
must
originate from the same source.
Digital Ground.
Ground point for internal digital circuits.
V
DDPLLA
+5.0 V
V
DDPLLP
68
+5.0 V
DGND
5, 8, 10, 15,
28, 36, 61
1, 49, 54, 58,
63, 66, 79
0.0 V
AGND
0.0 V
Analog Ground.
Ground point for internal analog circuits. DGND and
AGND should be connected to the same ground plane.
Pin Descriptions
(continued)
Pin Name
Pin Number
Type/
Value
Pin Function Description
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