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參數(shù)資料
| 型號： | TMC2360 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | VGA to NTSC/PAL Video Output Processor(VGA 到NTSC/PAL 視頻輸出處理器) |
| 中文描述： | VGA轉(zhuǎn)NTSC / PAL視頻輸出處理器（顯卡到的NTSC / PAL視頻輸出處理器） |
| 文件頁數(shù)： | 10/24頁 |
| 文件大?。?/td> | 230K |
| 代理商： | TMC2360 |
TMC2360
PRODUCT SPECIFICATION
10
Table 9. Display Power Management Signaling (DPMS) States
Table 10. TVSTD Control When Under Software Control (VSCOM = 1)
State
On
Stand-by
Suspend
Off
VGAHS
Pulses
No Pulses
Pulses
No Pulses
VGAVS
Pulses
Pulses
No Pulses
No Pulses
TMC2360 State
On, video active
Stand-by, screen blanked (color set by BLUE)
Stand-by, screen blanked (color set by BLUE)
Off, screen black (equivalent to PWRDN, except A/D Clock
and 27MHZ oscillator are active.)
TVSTD
1-0
XX
X0
01
11
0X
10
11
XX
Hsyncs per Vsync Interval
10,11,12
6,7,9
6,7,9
6,7,9
1-5,8,14,15
1-5,8,14,15
1-5,8,14,15
0,13
Television Standard
PAL 800 (B, G, I)
PAL 640 (B, G, I)
PAL-M
(reserved)
NTSC-EIAJ
NTSC
(reserved)
Blank (with prior standard)
VGA Frame Rate
50 Hz
50 Hz
60 Hz
60 Hz
60 Hz
50/60 Hz
Table 11. VSCOM Filter Command
Interpretation (VSCOM=1)
Microprocessor Interface
Table 12 shows the five registers that may be read after the
Address Register has been loaded. Only the two VGA regis-
ters and the Address Register may be written. For micropro-
cessor control, 40h must be written into VGA register 1. To
disable control through VGA Register 0, 00h must be written
into register 1. Bit assignments of VGA register 0 are listed
in Table 13. Bit assignments of VGA register 1 are listed in
Table 14.
For communications through the microprocessor port, set
MPEN = HIGH. Read and write timing is shown in Figure 3
and Figure 4
.
To access a VGA register, write the address of
the selected register into the lower four bits of the eight bit
Address Register with A
0
= LOW. Then with A
0
= HIGH,
read or write to the selected register.
HSYNCs per VSYNC
Interval
5, 9, 12
4, 7, 11
1, 2, 3, 6, 8, 10, 14, 15
0, 13
Filter Mode
No Filter
2-line filter
3-line filter
Blank (with prior mode)
Table 12. Microprocessor Addressable
Registers
Table 13. VGA Control Register 0 Bit Map
A1
0
0
0
0
0
A0
0
1
1
1
1
Address
Register Value
x
x0
x1
x6
x7
Register
Address Register
VGA Register 0
VGA Register 1
Revision ID (xxh)
Part ID (0Fh)
Bit #
7
6-5
Name
—
FIL
Function
0 (reserved)
0 0 No Filter
0 1 2-line Filter
1 x 3-line Filter
0 0 0 NTSC-EIA
0 0 1 NTSC
0 1 0 PALM
0 1 1 PAL640
1 x x PAL800
0 0 Black
0 1 Ramp
1 0 Color Bars
1 1 Normal
4-2
TVSTD
1-0
VIDEO
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