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參數(shù)資料
| 型號： | TMC2360 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | VGA to NTSC/PAL Video Output Processor(VGA 到NTSC/PAL 視頻輸出處理器) |
| 中文描述： | VGA轉(zhuǎn)NTSC / PAL視頻輸出處理器（顯卡到的NTSC / PAL視頻輸出處理器） |
| 文件頁數(shù)： | 4/24頁 |
| 文件大小： | 230K |
| 代理商： | TMC2360 |
TMC2360
PRODUCT SPECIFICATION
4
VGAVS
45
CMOS
S
VGA Vertical Sync.
Incoming VGA sync may be of either polarity
(active LOW or active HIGH). The VGAVS pin has a light pull-up and
a Schmitt trigger.
Buffered Horizontal Sync Output.
Follows VGAHS.
Buffered Vertical Sync Output.
Follows VGAVS.
HSOUT
VSOUT
Global Controls
TVSTD
1-0
27
26
TTL
TTL
39, 40
CMOS
P
Video Output Standard Select.
Preprogrammed into the TMC2360
are timing, subcarrier frequency and phase parameters
corresponding to worldwide NTSC and PAL standards. TVSTD
1-0
select one of four sets of parameters to set up the encoder. Frame
rate of the graphics source must be twice the frame rate of the
selected video standard.
Resolution Select for PAL.
Sets number of samples per VGA line.
Display Power Management Signaling Enable.
When HIGH, the
operational state of the TMC2360 is controlled by the pulse activity on
VGAHS and VGAVS. When LOW, the state of the TMC2360 is
controlled only by input pins.
Flicker Filter Mode Select.
The adaptive flicker reduction filter may
be configured for HIGH filtering, MEDIUM filtering, or NO filtering by
pulsing this input HIGH. FIL defaults to HIGH-filter mode upon power-
up. If VSCOM is HIGH, the filter mode will be selected by the
pulsewidth of VGAVS, and FIL will be ignored. The FIL input is a
Schmitt trigger.
Vertical Sync Communications Enable.
When HIGH, vertical sync
pulse width (VGAVS) will control the filter mode, and FIL will be
ignored.
Power-Down Control.
When HIGH, the TMC2360 is fully operational
and enabled. When LOW, the TMC2360 is configured for minimum
power consumption. D/A converters and clocks are disabled.
Previously established set-up conditions are retained and remain in
effect when PWRDN goes HIGH.
Reset.
Initializes internal registers.
Sampling Phase Control.
Shifts the A/D sampling phase by 180
°
.
Set Phase = LOW.
PAL800
DPMS
41
43
CMOS
P
CMOS
P
FIL
42
CMOS
S
VSCOM
44
CMOS
P
PWRDN
72
CMOS
P
RESET
PHASE
71
6
CMOS
P
CMOS
P
Encoder Controls
CVIDEN
74
CMOS
P
Composite Video D/A Power Enable.
When HIGH, the
COMPOSITE D/A converter is enabled. When LOW it is disabled to
save power.
S-Video D/A Power Enable.
When HIGH, the CHROMA and LUMA
D/A converters are enabled. When LOW, they are disabled to save
power.
Blank Screen Generator.
When HIGH, the color selected by BLUE
is displayed on the screen. When LOW, incoming video from the
internal FIFO is encoded.
Blank Screen Color Selector.
When HIGH, the screen will be
blanked to blue when BLANK is HIGH. When LOW, the screen will be
blanked to black when BLANK is HIGH.
SVIDEN
73
CMOS
P
BLANK
38
CMOS
P
BLUE
37
CMOS
P
Pin Descriptions
(continued)
Pin Name
Pin Number
Type/
Value
Pin Function Description
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