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參數(shù)資料
| 型號： | TMC2302AKEC1 |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 數(shù)字信號處理外設(shè) |
| 英文描述： | Image Manipulation Sequencer |
| 中文描述： | 16-BIT, DSP-ADDRESS SEQUENCER, PQFP120 |
| 封裝： | METRIC, QFP-120 |
| 文件頁數(shù)： | 26/36頁 |
| 文件大?。?/td> | 188K |
| 代理商： | TMC2302AKEC1 |
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TMC2302A
PRODUCT SPECIFICATION
26
P
In the following discussion, the TMC2302A address outputs
SADR
X
and SADR
Y
will be designated as:
Interpolation Kernel
Figure 13. TMC2302A Serial Walk Sequence in real time
bilinear resampling, this is executed in parallel
When the transformation polynomial is evaluated and the
resulting pixel address falls within a group of four nearby
pixels (non-integer result), the TMC2302A will always
choose the upper leftmost pixel (P
ij
) as the nearest neighbor
(due to the fractional address truncation in the X and Y direc-
tions). Since the four pixels will reside in independent banks,
the upper leftmost pixel might be located in any of the four
memory banks (A,B,C, or D). The bank which contains the
nearest neighbor must be known, since in each case, different
memory address modification is required to select the correct
pixel from each bank.
Horizontal Source
XA
0
Least-Significant Horizontal Source X-Address
Bit SADR
X
(8)
XA
m
Upper Horizontal Source Address Bits SADR
X
(19:9)
YA
0
Least-Significant Vertical Source Y-Address Bit
SADR
X
(8)
Ya
m
Upper Vertical-Source Address Bits SADR
Y
(19:9)
Figure 14. Possible Selections for Nearest Neighbor
Memory Address Modification
Using the address LSBs (XA
0
, YA
0
) from each TMC2302A
external logic can determine which bank contains the nearest
neighbor. (This same decoding is used when loading the
original image into the source image RAMs.)
Case* XA
0
YA
0
Nearest Neighbor (Upper Leftmost)
Pixel
1
0
0
A Memory Bank contains Nearest
Neighbor
2
1
0
B Memory Bank contains Nearest
Neighbor
3
0
1
C Memory Bank contains Nearest
Neighbor
4
1
1
D Memory Bank contains Nearest
Neighbor
*from Figure 14 above
65-2302-17
*-1
*-2
*-3
*-4
B
A
B
A
B
A
B
C
D
C
D
C
D
D
B
A
B
A
B
A
B
D
C
D
C
D
C
D
TMC2302A Ad-
dress
XA
m
,
0
0
0
0
1
1
1
255
255
Bank A
Bank B
Bank C
Bank D
YA
m
XA
0
YA
0
= 00
XA
0
YA
0
= 10
XA
0
YA
0
= 01
XA
0
YA
0
= 11
0
1
2
255
0
1
2
254
255
A
0,0
A
0,1
A
0,2
A
0,255
A
1,0
A
1,1
A
1,2
A
255,254
A
255,254
B
0,0
B
0,1
B
0,2
B
0,255
B
1,0
B
1,1
B
1,2
B
255,254
B
255,254
C
0,0
C
0,1
C
0,2
C
0,255
C
1,0
C
1,1
C
1,2
C
255,254
C
255,254
D
0,0
D
0,1
D
0,2
D
0,255
D
l,0
D
1,1
D
1,2
D
255,254
D
255,254
P
i, j
P
i, j+1
* - actual Pixel
P
i+1, j
P
i+1, j+1
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| TMC2330AH5C | Coordinate Transformer 16 x 16 Bit, 40 MOPS |
| TMC2330AH5C1 | Coordinate Transformer 16 x 16 Bit, 40 MOPS |
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| TMC2330AG1C | Coordinate Transformer 16 x 16 Bit, 40 MOPS |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| TMC2330A | 制造商:CADEKA 制造商全稱:CADEKA 功能描述:Coordinate Transformer 16 x 16 Bit, 40 MOPS |
| TMC2330AG1C | 制造商:CADEKA 制造商全稱:CADEKA 功能描述:Coordinate Transformer 16 x 16 Bit, 40 MOPS |
| TMC2330AG1C1 | 制造商:CADEKA 制造商全稱:CADEKA 功能描述:Coordinate Transformer 16 x 16 Bit, 40 MOPS |
| TMC2330AH5C | 制造商:CADEKA 制造商全稱:CADEKA 功能描述:Coordinate Transformer 16 x 16 Bit, 40 MOPS |
| TMC2330AH5C1 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Coordinate Transformer 16 x 16 Bit, 40 MOPS |
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