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參數(shù)資料
| 型號： | TMC2302AKEC1 |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 數(shù)字信號處理外設(shè) |
| 英文描述： | Image Manipulation Sequencer |
| 中文描述： | 16-BIT, DSP-ADDRESS SEQUENCER, PQFP120 |
| 封裝： | METRIC, QFP-120 |
| 文件頁數(shù)： | 12/36頁 |
| 文件大?。?/td> | 188K |
| 代理商： | TMC2302AKEC1 |
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TMC2302A
PRODUCT SPECIFICATION
12
P
XMIN,
XMAX
The source image boundaries are defined for
each device by the parameters XMIN and
XMAX, in the case of the row device.
The column device then contains YMIN and
YMAX, and the page device (in systems
performing three-dimensional operations)
ZMIN and ZMAX. The value of XMAX
should be greater than XMIN if the boundary
violation flag SVAL is to operate correctly.
These values are assumed to be in 32-bit
unsigned binary integer format.
PFLS
The user can set the number of clock cycles
that the TMC2302A continues in to the next
image following the DONE flag, allowing his
system to Flush all control and data pipeline
paths and halt after a maximum of seven
cycles. The numeric format assumed is three-
bit unsigned binary integer.
PTAD,
PDON,
PEND,
PTVA,
PSVA,
PTWR,
PACC
As mentioned above, the control signals and
target image pixel addresses generated by the
TMC2302A can be delayed up to seven clock
cycles after the nominal timing shown in
Table 4 by setting the appropriate Pipeline
delay word. The numeric format assumed for
all delay words is three-bit unsigned binary
integer.
XTND
When the user sets the control bit XTND to 1,
the TMC2302A operates in an extended-
resolution source address bus configuration.
Assuming that the user has his own raster scan
generator available elsewhere to manage the
flow of output pixels from the TMC2302A
system, the target address output bus TADR
11-0
is reconfigured internally into an extension of
the source address bus, as SADR
11-0
. The
original source address bus SADR
23-0
is then
SADR
35-12
, providing 36 bits of spatial reso-
lution in the source address space. An XTND
of 0 puts the device in the standard 24-bit
source, 12-bit target address configuration.
E3D
Setting this control bit to 0 indicates a
two-dimensional image transform is to be
performed. When the E3D is set to 1, a three-
dimensional image is assumed, using three
TMC2302A devices.
DIM
The user sets each TMC2302A to operate in a
specific dimension as follows:
DIM
1,0
00
01
10
11
Dimension
X/U (Row) Device
Y/V (Column) Device
Z/W (Page) Device
No Operation
MODE
In systems performing the standard two-dimen-
sional spiral interpolation walk, MODE is set
to 11, indicating single-pass operation. When
performing multiple-pass resampling, the user
must set this two-bit control word pass-by-pass
in all IMSs, to implement each pass direction.
For instance, setting MODE to 00 causes the
TMC2302A system to increment only in the
X-direction, holding the Y (and Z) addresses
constant until the end of that pixel walk. On the
next pass through the image, the user sets
MODE = 01, with the kernel increment in Y
only. In 3D, the IMS system then proceeds again
through the (U, V) target image space, walking
kernels only along the Z direction.
Mode
1,0
00
01
10
11
Resampling Performed
X-Pass
Y-Pass
Z-Pass
Two-Dimension Spiral Walk
KERNEL This parameter determines the size of the inter-
polation walk performed. To implement a
convolutional sum of K+1 pixels, the parameter
KERNEL is set to K, up to a maximum of 255.
In single-pass operation, this value must be
identical in all devices, giving a square interpo-
lation kernel. In multiple-pass operation, how-
ever, non- square kernels may be implemented,
with different K values in each dimension. Or,
the user could utilize a banded memory architec-
ture in two-pass mode to access an entire row or
column of a kernel in one clock, completing the
entire sum in a single pass through the other
dimension of the kernel. Numeric format is 8-bit
unsigned integer.
FOV
The user determines the size of each step in an
interpolation walk, in terms of the number of
source image pixels, by setting the Field Of
View control. The binary weighting of the image
transformation parameters and source address
must be taken into account when determining
this value. See Table 6 and the Applications
Discussion section. The numeric format
assumed is unsigned 16-bit integer.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TMC2330AH5C | Coordinate Transformer 16 x 16 Bit, 40 MOPS |
| TMC2330AH5C1 | Coordinate Transformer 16 x 16 Bit, 40 MOPS |
| TMC2330A | Coordinate Transformer 16 x 16 Bit, 40 MOPS |
| TMC2330AG1C | Coordinate Transformer 16 x 16 Bit, 40 MOPS |
| TMC2330AG1C1 | Coordinate Transformer 16 x 16 Bit, 40 MOPS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TMC2330A | 制造商:CADEKA 制造商全稱:CADEKA 功能描述:Coordinate Transformer 16 x 16 Bit, 40 MOPS |
| TMC2330AG1C | 制造商:CADEKA 制造商全稱:CADEKA 功能描述:Coordinate Transformer 16 x 16 Bit, 40 MOPS |
| TMC2330AG1C1 | 制造商:CADEKA 制造商全稱:CADEKA 功能描述:Coordinate Transformer 16 x 16 Bit, 40 MOPS |
| TMC2330AH5C | 制造商:CADEKA 制造商全稱:CADEKA 功能描述:Coordinate Transformer 16 x 16 Bit, 40 MOPS |
| TMC2330AH5C1 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Coordinate Transformer 16 x 16 Bit, 40 MOPS |
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