參數(shù)資料
型號(hào)： TMC2302AKEC1
廠商： FAIRCHILD SEMICONDUCTOR CORP
元件分類(lèi)： 數(shù)字信號(hào)處理外設(shè)
英文描述： Image Manipulation Sequencer
中文描述： 16-BIT, DSP-ADDRESS SEQUENCER, PQFP120
封裝： METRIC, QFP-120
文件頁(yè)數(shù)： 23/36頁(yè)
文件大?。?/td> 188K
代理商： TMC2302AKEC1
PRODUCT SPECIFICATION
TMC2302A
23
P
The TMC2302A Image Manipulation
Sequencer
The TMC2302A is a controller/address generator, around
which an image filtering and resampling system can be built.
Under limited supervision from an external controller, the
TMC2302A will generate the sequence of memory read and
write addresses to transform, resample, and/or filter an
image. In all cases, it fetches data from one image buffer,
governs its convolution with a user-specified kernel of
coefficients, and directs the results to another image memory
space. With 24-bit source address buses the device can
operate from a source frame size of, for example,
64K X 64K pixels with spatial resolution of 1/256th pixel. A
simplified block diagram of the TMC2302A is shown in
Figure 9. Although the 24 source addresses bits of each
TMC2302A can be designed arbitrarily with the source
image address bus, assume for the current discussion that
bits SADR (19:8) will correspond to the source image
address and that SADR (7:4) therefore denote subpixel post-
poning to 1/16 pixel resolution.
The basic 2-D system, shown in Figure 10, consists of data
source and destination memories, coefficient lookup table,
multplier-accumulator, TMC2302A parameters to define the
transform and starts the operation. It may also control the
loading of the source image into RAM and provide the
screen refresh, if needed.
Figure 9. TMC2302A Block Diagram
65-2302-15
ASYNCHRONOUS
HOST INTERFACE
IDAT
15-0
IADR
6-0
ICS
IWR
CONTROL
PARAMETER
REGISTERS
CONTROL
NOOP
SYNCHRONOUS
HOST INTERFACE
INIT
CLK
SYNC
TARGET
ADDRESS
GENERATOR
SOURCE
ADDRESS
GENERATOR
SOURCE MEMORY
INTERFACE
CONVOLUTIONAL
CONTROL
TARGET
MEMORY
INTERFACE
SYNC FLAGS
OES
SADR
23-0
SVAL
OEK
ACC
TWR
KADR
7-0
OET
TVAL
TADR
11-0
END
DONE
WALK
COUNTER
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