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參數(shù)資料
| 型號： | TMC2302AH5C1 |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 數(shù)字信號處理外設(shè) |
| 英文描述： | Image Manipulation Sequencer |
| 中文描述： | 16-BIT, DSP-ADDRESS SEQUENCER, PPGA120 |
| 封裝： | CAVITY-UP, PLASTIC, PGA-120 |
| 文件頁數(shù)： | 29/36頁 |
| 文件大?。?/td> | 188K |
| 代理商： | TMC2302AH5C1 |
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PRODUCT SPECIFICATION
TMC2302A
29
P
Figure 20. Intrapixel Resolution
16 STEPS/PIXEL
65-2302-17
16 STEPS
Pi, j+1
Pi, j
Pi +1, j
Pi +1, j+1
256 Discrete
Coefficient Values
Similar to determining the correct four pixel group, the coef-
ficients must take into account the memory bank (A, B, C, or
D) that contains the upper leftmost pixel, and adjust the coef-
ficients accordingly. These adjustments are necessary since
the fractional address outputs (SADR
X
7:4), SADR
Y
(7,4)
from the TMC2302As reflect the spatial distance only from
the upper leftmost pixel within the pixel group. Assuming
that the fractional addresses SADR
X
(7:4) and SADR
Y
(7:4)
plus the integer LSBs SADR
X
(8) and SADR
Y
(8) are to be
used directly to address the 1024-byte coefficient memory,
the loading of the coefficients is shown below with F
X
=
SADR
X
(7:4) and F
Y
= SADR
Y
(7:4) Case A through D are
the same as discussed previously for the pixel address modi-
fications.
Case A:
A is nearest neighbor (XA
0
= 0, YA
0
= 0)
Coeff A = (1 - f
X
) * (1 - f
Y
)
Coeff B = (f
X
) *(1 - f
Y
)
Coeff C = (1 - f
X
) * (f
Y
)
Coeff D = f
X
* f
Y
Case B:
B is nearest neighbor (XA
0
= 1, YA
0
= 0)
Coeff A = f
X
* (1-f
Y
)
Coeff B =(1-f
X
) * (1-f
Y
)
Coeff C = f
X
* f
Y
Coeff D = (l-f
X
)f
Y
Case C:
C is nearest neighbor (XA
0
= 0, YA
0
= 1)
Coeff A = (1- f
X
) f
Y
Coeff B = f
X
f
Y
Coeff C = (1 - f
X
) (1 - f
Y
)Coeff D = f
X
* (1 - f
Y
)
Case D:
D is nearest neighbor (XA
0
= 1, YA
0
= 1)
Coeff A = f
X
f
Y
Coeff B = (1 - f
X
)f
Y
Coeff C = f
X
* (1 - f
Y
)
Coeff D = (1 - f
X
) (1 - f
Y
)
Incorporating the concepts outlined in this discussion, the
final system for one-cycle blinear interpolation is shown in
Figure 21. This figure shows a small increase in logic over
the basic 2-D system shown in Figure 10. The additional
logic required includes: TMC2246 (rather than a single mul-
tiply/accumulate), and three additional coefficient memories.
Some additional decoding logic is required to load the four
pixel memory banks as well as some data and address pipe-
lining (registering) to meet timing requirements. The solu-
tion, however, provides an increased pixel bandwidth, by a
factor of four, and only a small increase in part count.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TMC2302AKEC | Image Manipulation Sequencer |
| TMC2302AKEC1 | Image Manipulation Sequencer |
| TMC2330AH5C | Coordinate Transformer 16 x 16 Bit, 40 MOPS |
| TMC2330AH5C1 | Coordinate Transformer 16 x 16 Bit, 40 MOPS |
| TMC2330A | Coordinate Transformer 16 x 16 Bit, 40 MOPS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TMC2302AKEC | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Image Manipulation Sequencer |
| TMC2302AKEC1 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Image Manipulation Sequencer |
| TMC2330A | 制造商:CADEKA 制造商全稱:CADEKA 功能描述:Coordinate Transformer 16 x 16 Bit, 40 MOPS |
| TMC2330AG1C | 制造商:CADEKA 制造商全稱:CADEKA 功能描述:Coordinate Transformer 16 x 16 Bit, 40 MOPS |
| TMC2330AG1C1 | 制造商:CADEKA 制造商全稱:CADEKA 功能描述:Coordinate Transformer 16 x 16 Bit, 40 MOPS |
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