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參數(shù)資料
| 型號： | TMC2302AH5C1 |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 數(shù)字信號處理外設(shè) |
| 英文描述： | Image Manipulation Sequencer |
| 中文描述： | 16-BIT, DSP-ADDRESS SEQUENCER, PPGA120 |
| 封裝： | CAVITY-UP, PLASTIC, PGA-120 |
| 文件頁數(shù)： | 28/36頁 |
| 文件大?。?/td> | 188K |
| 代理商： | TMC2302AH5C1 |
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TMC2302A
PRODUCT SPECIFICATION
28
P
Note: Only modifications to the source image memory are
necessary. The destination image memory may be arranged
in a linear or other type array as required by the refresh
circuitry.
Coefficient Memory
Typically, the 4 highest fractional source address bits from
each TMC2302A (SADR (7:4) in the example) are used to
reflect the offset from the nearest XA (YA) pixel location.
With spatial resolution of 4 bits in both the X and Y direc-
tions, there can be as many as 256 unique coefficient values.
This requires a coefficient memory of at least 256 bytes.
However, as shown below, each of the four different cases
requires its own set of 256 coefficients.
One-cycle bilinear interpolation requires four independent
coeffficient memories, so that a parallel multiplication can be
performed with the four pixel values.
Figure 19. Memory Address Modification
65-2302-18
TMC2302A
(ROW)
SADR (19:9)
SADR (8)
TADR (11:0)
TMC2302A
(COLUMN)
YA
μ
YAO
V
BANK A
X11-1
ADDRESS IN
Y11-1
11
11
OUT
8*
TO MPY A
BANK C
X11-1
Y11-1
OUT
8
TO MPY C
BANK B
X11-1
Y11-1
OUT
8
TO MPY B
BANK D
X11-1
Y11-1
OUT
8
TO MPY D
TO
DEST.
MEMORY
11
11
12
12
U
XA
μ
XA0
TADR (11:0)
SADR (19:9)
SADR (8)
U
*Number of bits of intensity per pixel, per column component, typically 8 to 12.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TMC2302AKEC | Image Manipulation Sequencer |
| TMC2302AKEC1 | Image Manipulation Sequencer |
| TMC2330AH5C | Coordinate Transformer 16 x 16 Bit, 40 MOPS |
| TMC2330AH5C1 | Coordinate Transformer 16 x 16 Bit, 40 MOPS |
| TMC2330A | Coordinate Transformer 16 x 16 Bit, 40 MOPS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TMC2302AKEC | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Image Manipulation Sequencer |
| TMC2302AKEC1 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Image Manipulation Sequencer |
| TMC2330A | 制造商:CADEKA 制造商全稱:CADEKA 功能描述:Coordinate Transformer 16 x 16 Bit, 40 MOPS |
| TMC2330AG1C | 制造商:CADEKA 制造商全稱:CADEKA 功能描述:Coordinate Transformer 16 x 16 Bit, 40 MOPS |
| TMC2330AG1C1 | 制造商:CADEKA 制造商全稱:CADEKA 功能描述:Coordinate Transformer 16 x 16 Bit, 40 MOPS |
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