參數(shù)資料
型號(hào)： TMC2302A
廠商： Fairchild Semiconductor Corporation
英文描述： Image Manipulation Sequencer
中文描述： 圖像處理序列
文件頁數(shù)： 27/36頁
文件大小： 188K
代理商： TMC2302A
PRODUCT SPECIFICATION
TMC2302A
27
P
Addressing for each memory bank (A, B, C, D) is done
using the uppermost address bits (XA
m
) of the TMC2302As.
The LSB of each TMC2302A is used to determine both the
upper leftmost pixel and the address modification required.
In the following paragraphs, the lower case subscripts (i,j)
denote the address of a pixel within a given memory bank
(A, B, C, or D), and XA, YA are used to denote physical
address outputs of the TMC2302A pairs.
Pixel address modification use to access the correct four
pixel group is determined as follows:
Case A:
A
i,j
is nearest upperleft neighbor,
(No address modifications)
(XA
0
= YA
0
= 0)
A
i,j
B
i,j
*
C
i,j
D
i,j
Figure 15. Pixel Memory Mapping for A = Upper Leftmost
Memory Addressing Becomes:
A address = XA
m
, YA
m
B address = XA
m
, YA
m
C address = XA
m
, YA
m
D address = XA
m
, YA
m
i.e., no modification is required.
Case B:
B
i,j
is upperleft neighbor,
(Modify X component of A & C memory addresses)
(XA
0
= 1, YA
0
= 0)
B
i,j
A
i + 1,j
*
D
i,j
C
i + 1,j
Figure 16. Pixel Memory Pattern for B = Upper Leftmost
Memory Addressing Becomes:
A address = (XA
m
+ 1, YA
m
)
B address = (XA
m
, YA
m
)
C address = (XA
m
+ 1, Ya
m
)
D address = (XA
m
YA
m
)
Case C:
Ci,j is upperleft neighbor,
(Modify Y component of A & B memory addresses)
(XA
0
= 0, YA
0
= 1)
C
i,J
D
i,j
*
A
i,j + 1
B
i, j + 1
Figure 17. Pixel Pattern for C = Upper Leftmost
Memory Addressing Becomes:
A address = XA
m
YA
m
+ 1
B address = XA
m
, Ya
m
+ 1
C address = XA
m
, YA
m
D address = XA
m
, YA
m
Case D:
Di,j is the nearest neighbor
(Modify A, B & C addresses, X and Y components)
(XA
0
= 1, YA
0
= 1)
D
i,j
C
i + 1,j
*
B
i, j + 1
A
i +1,j +1
Figure 18. Pixel Pattern for D = Upper Leftmost
Memory Addressing Becomes:
A address = XA
m
+ 1, YA
m
+ 1
B address = XA
m
, Ya
m
+
1
C
address = XA
m
+ 1, YA
m
D address = XA
m
,
YA
m
Taking a close look at the address modifications required for
each case above, a simple pattern can be seen. This pattern
leads to a set of address modification “rules” based on the
values of the least-signficant address bits from the
TMC2301s (XA
0
and YA
0
). These rules are:
When YA
0
= 0. (Case A & B)
No modificaton to the Y address component (YA
m
) is
necessary.
When YA
0
= 1, (Case C & D)
The Y component (YA
m
) of addresses to the A & B memory
banks must be incremented by 1.
When XA
0
= 0. (Case A & C)
No modification to the X address component (XA
m
) is
necessary.
When XA
0
= 1, (Case B & D)
The X component (XA
m
,) of addresses to the A & C memory
banks must be incremented by 1.
A system can easily be designed to modify the pixel memory
addresses according to the above criteria, to select the correct
four pixels to be interpolated. Rather than actually perform-
ing a “conditional” address increment as discussed above.
It requires less logic simply to add the LSB address bit to the
memory bank addresses (XA
m
, YA
m
). Figure 12 shows the
logic to perform the required address modifications.
The addition (XA
m
, + XA
0
, YA
m
, +YA
0
) can be done
using half-adders with the XA
0
(YA
0
) address output of the
TMC2302A connected to the carry-in of each adder. It can
also be done using high-speed programmable logic.
相關(guān)PDF資料
PDF描述
TMC2302AH5C Image Manipulation Sequencer
TMC2302AH5C1 Image Manipulation Sequencer
TMC2302AKEC Image Manipulation Sequencer
TMC2302AKEC1 Image Manipulation Sequencer
TMC2330AH5C Coordinate Transformer 16 x 16 Bit, 40 MOPS
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TMC2302AH5C 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Fairchild Semiconductor Corporation 功能描述:
TMC2302AH5C1 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Fairchild Semiconductor Corporation 功能描述:
TMC2302AKEC 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Image Manipulation Sequencer
TMC2302AKEC1 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Image Manipulation Sequencer
TMC2330A 制造商:CADEKA 制造商全稱:CADEKA 功能描述:Coordinate Transformer 16 x 16 Bit, 40 MOPS
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