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參數(shù)資料
| 型號： | TMC2302A |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Image Manipulation Sequencer |
| 中文描述： | 圖像處理序列 |
| 文件頁數(shù)： | 24/36頁 |
| 文件大?。?/td> | 188K |
| 代理商： | TMC2302A |
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TMC2302A
PRODUCT SPECIFICATION
24
P
Figure 10. Basic 2-D Image Transformation Systems
65-2302-16
2302A ROW
(X)
SADR
19-8
COEFF.
BUFFER
RAM
1024 x 8
2302A
COLUMN (Y)
CLOCK
12
DATA
CONTROL
TADR
11-0
ADDRESS
12
SOURCE
ADDRESS
24
SOURCE
IMAGE
BUFFER
RAM
8
DATA IN
8
HERE
4 X 4K WORDS
IMAGE SIZE
ONE SET
PER COLOR
COMPONENT
(Not recommended
for composite video)
ONE SET
PER COLOR
COMPONENT
8
ONE SET
PER COLOR
COMPONENT
8
DATA OUT
24
12
SADR
19-8
TADR
11-0
SADR
7-4
KADR
1-0
CLK
X,Y,P
X
8 x 8
MAC
DOUT
8
Y
DESTINATION
IMAGE
BUFFER
RAM
DESTINATION
ADDRESS
ADDRESS
6
4
A
A
Inexact Transformations
In many cases, evaluation of the transformation polynomial
results in a non-integer result (non-integer address in the X,
Y image space). In such cases, the mapping from original
image to transformed image will be inexact. When this
occurs, the user has the option of accepting the pixel “near-
est” to the address generated, or performing interpolation,
a weighted average of nearby pixel values. Using the pixel
nearest the address generated is the fastest method since one
transformed pixel can be generated on every cycle.
The resulting image will include jagged biasing artifacts,
however. Performing several transformations on the same
image will further degrade the resulting image.
One Cycle Bilinear Interpolation
A better image can be obtained by finding the four pixels
nearest the address generated and performing a weighted
averaging to determine the new pixel value. This is known as
bilinear interpolation. The TMC2302A eases the control
logic required for such a function by performing a “walk”
around the four closest pixels in the source image space.
Essentially, the TMC2302A generates the addresses of the
four walk cycles, and the current source pixel is multiplied
by a weighting factor and accumulated by the external multi-
plier accumulator. At the end of the walk, the accumulated
result from the four nearest pixels is written into the destina-
tion image RAM and the TMC2302A proceeds to the next
group. The obvious disadvantage to using bilinear interpola-
tion is that one new destination pixel is generated only on
every fourth cycle, reducing the output bandwidth by a factor
of four.
One method of “real-time” bilinear interpolation consists of
using four memories, each containing the entire source
image. The storage arrangement of the pixels within each
bank is staggered so that a single address fed to the memories
will result in the access of the proper four pixel group.
The TMC2302A is programmed to generate the nearest
neighbor address and the four nearest pixels are accessed
simultaneously and input to the four independent multipliers
of a TMC2246 quad multiplier chip. The four pixels are mul-
tiplied by their associated weighting factors and added to
determine the destination pixel sum. The major drawback of
this method is the prohibitive cost for additional memory
required to store four copies of the entire source image.
For large images, the memory cost and additional board
space makes this method unattractive.
相關PDF資料 |
PDF描述 |
|---|---|
| TMC2302AH5C | Image Manipulation Sequencer |
| TMC2302AH5C1 | Image Manipulation Sequencer |
| TMC2302AKEC | Image Manipulation Sequencer |
| TMC2302AKEC1 | Image Manipulation Sequencer |
| TMC2330AH5C | Coordinate Transformer 16 x 16 Bit, 40 MOPS |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TMC2302AH5C | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Fairchild Semiconductor Corporation 功能描述: |
| TMC2302AH5C1 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Fairchild Semiconductor Corporation 功能描述: |
| TMC2302AKEC | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Image Manipulation Sequencer |
| TMC2302AKEC1 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Image Manipulation Sequencer |
| TMC2330A | 制造商:CADEKA 制造商全稱:CADEKA 功能描述:Coordinate Transformer 16 x 16 Bit, 40 MOPS |
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