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參數(shù)資料
| 型號： | TMC2243 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | 10 x 10 Bit, 20 MHz CMOS FIR(Finite Impulse Response) Filter(10 x 10 位,20 MHz CMOS 有限脈沖響應(yīng)濾波器) |
| 中文描述： | 10 × 10位，20兆赫的CMOS FIR（有限沖擊響應(yīng)）濾波器（10 × 10位，20兆赫的CMOS有限脈沖響應(yīng)濾波器） |
| 文件頁數(shù)： | 11/16頁 |
| 文件大?。?/td> | 120K |
| 代理商： | TMC2243 |
PRODUCT SPECIFICATION
TMC2243
11
Application Discussion
Loading and Updating of Coefficients
Because of the TMC2243’s internal architecture, its impulse
response is C
3
, C
2
, C
1
, where C
3
is the rightmost coefficient
and C
1
is the leftmost. However, for glitchless performance,
coefficients must be updated from left to right: C
1
then C
2
then C
3
.
For example, consider an adaptive filter whose first set of
coefficients is A
i
, second set is B
i
and third set is C
i
(Figure 4). First, the TMC2243 is initialized with A
i
. If these
are loaded in numerical (left to right) sequence, two of the
first three data points can be loaded with them, as shown in
Figure 4. Immediately after the third coefficient is loaded,
the first coefficient of the next set can be loaded, if desired,
along with the third data point.
Table 1. Impulse Response
Notes:
1. C
3
is she rightmost coefficient, C
1
is the leftmost
2. FT
1
is relevant only it SUMIN is used. When multiple chips
are cascaded, FT
1
LOW places a zero stage between their
concatenated impulse responses.
FT
3-1
000
001
010
011
100
101
110
111
Response
C
2
C
2
C
2
C
2
0
0
C
1
C
1
C
3
C
3
C
3
C
3
C
3
C
3
C
3
C
3
0
0
0
C
2
C
2
C
2
C
2
0
0
C
1
C
1
0
0
C
1
C
1
C
1
C
1
0
0
Building Longer Filters
To build a filter of more than three non-zero stages, merely
concatenate a series of TMC2243s. The coefficient inputs
may be connected to the data bus, a separate common coeffi-
cient bus, or separate buses, depending on system architec-
ture, memory and bus resources, and coefficient updating
requirements. The data inputs are connected to a common
bus. If the first feedthrough register is used (and a zero stage
is not desired there), an external register should be inserted
in the data input path for proper timing (Figure 9).
The 16-bit Sum-Out port of each TMC2243 is connected to
the Sum-In port of the next TMC2243 in the chain; the filter
output is the Sum-Out port of the last TMC2243. Since the 6
LSBs of each TMC2243’s accumulation pipeline are not out-
put, each TMC2243 incorporates a rounding increment of 1
into the sixth bit, to minimize bias.
When TMC2243s are cascaded in this fashion, the minimum
permissible clock period is the sum of the output delay and
the Sum-In port’s input setup time. When the Input Registers
are enabled (that is, FT
1
= LOW), full 20MHz performance
can be obtained.
All data and coefficient inputs and outputs are two's comple-
ment representation, whose relative scaling is presented in
the Data Formats table, Figure 1. Although the data values
are shown in fractional format, the user can arbitrarily
rescale them, as long as consistency is maintained.
AC Characteristics
Note:
1. All transitions are measured at a 1.5V level except for t
DIS
and t
ENA
.
Temperature Range
Standard
Min
Max
30
20
5
20
15
Extended
Min
Parameter
t
D
t
DC
t
HO
t
ENA
t
DIS
Test Conditions
V
DD
= Min, C
LOAD
= 40pF
V
DD
= Min, C
LOAD
= 10pF
V
DD
= Max, C
LOAD
= 40pF
V
DD
= Min, C
LOAD
= 40pF
V
DD
= Min, C
LOAD
= 40pF
Max
30
20
Units
ns
ns
ns
ns
ns
Output Delay
Output Delay, Cascaded
Output Hold Time
Three-State Output, Enable Delay
1
Three-State Output, Disable Delay
1
5
25
20
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