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參數(shù)資料
| 型號(hào)： | TMC2243 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | 10 x 10 Bit, 20 MHz CMOS FIR(Finite Impulse Response) Filter(10 x 10 位,20 MHz CMOS 有限脈沖響應(yīng)濾波器) |
| 中文描述： | 10 × 10位，20兆赫的CMOS FIR（有限沖擊響應(yīng)）濾波器（10 × 10位，20兆赫的CMOS有限脈沖響應(yīng)濾波器） |
| 文件頁(yè)數(shù)： | 6/16頁(yè) |
| 文件大?。?/td> | 120K |
| 代理商： | TMC2243 |
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TMC2243
PRODUCT SPECIFICATION
6
The basic equation describing the function of the TMC2243
operating in a fixed state is:
SO(N) = SI
(N – 6 + FT1 + FT2 + FT3)
1
x DI
(N – 7 + FT2 + FT3)
2
x DI
(N – 5 + FT3)
3
x DI
(N – 3)
+ C
+ C
+ C
Careful observation of the clock delays shown is basic to
construction of a filter algorithm. The operating sequence for
the common application with FT
is shown in Figure 2. The simplified block diagram demon-
strates the clock stages in this configuration. When
FT
1
= HIGH, the input feedthrough register is bypassed, and
care must be taken to observe the setup requirements on the
input of the first adder. Due to the absence of the input regis-
ter buffer, note that the adder operates on data stable just
prior to the arrival of the next clock, and not that setup at the
rising edge of the current clock. When FT
register latches the input data, and the Sum Input follows
1-3
= HIGH (no zero stages)
1
= LOW the input
setup and hold requirements similar to the other registered
inputs of the TMC2243. When FT
anteed to allow 20MHz pipelined operation, assuming that
input setup is observed, including cascaded operation. See
the AC Characteristics table and Figure 9 in the Applications
Discussion section.
1
= HIGH, t
S(SI)
is guar-
Figure 3 shows the effects of the feedthrough registers on fil-
ter operation, with two different configurations. The inputs
are those presented at the corresponding rising edge of clock,
excepting the delayed setup requirements of the Sum Input
when FT
1
= HIGH. The outputs are those available up to and
including the corresponding edge of clock. Applications uti-
lizing the TMC2243's ability to modify coefficients dynami-
cally are demonstrated in Figure 4, showing the operation of
a typical adaptive filter. Note that the Sum Output will be
zero in the first few clock cycles of all examples only if the
Coefficient Registers are initialized to zero beforehand.
Figure 3. Impulse Response Filter Operation Sequence with FT
2,3
= LOW
Cycle
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
SI(A) FT
1
0
0
0
= LOW
SI(B) FT
1
0
0
0
0
= HIGH
DI
0
0
0
DI
DI
1
D1
2
DI
3
DI
4
DI
5
DI
6
DI
7
DI
8
DI
9
0
0
0
0
0
0
0
0
CI
K0
K1
K2
0
0
0
0
K
0
'
0
K
1
'
0
K
2
'
0
0
0
0
0
0
0
0
0
CWE
01
10
11
00
00
00
00
01
00
10
00
11
00
00
00
00
00
00
00
00
00
SO
X
X
X
X
0
0
DI
0
K
2
DI
1
K
2
DI
0
K
1
+ DI
2
K
2
SI
0
+ DI
1
K
1
+ DI
3
K
2
SI
1
+ DI
0
K
0
+ DI
2
K
1
+ DI
4
K
2
SI
2
+ DI
1
K
0
+ DI
3
K
1
+ DI
5
K
2
SI
3
+ DI
2
K
0
+ DI
4
K
1
+ DI
6
K
2
SI
4
+ DI
3
K
0
+ DI
5
K
1
+ DI
7
K
2
SI
5
+ DI
4
K
0
+ DI
6
K
1
+ DI
8
K
2
SI
6
+ DI
5
K
0
' + DI
7
K
1
' + DI
9
K
2
′
SI
7
+ DI
6
K
0
' + DI
8
K
1
′
SI
8
+ DI
7
K
0
' + DI
9
K
1
′
SI
9
+ DI
8
K
0
′
DI
9
K
0
′
0
SI
SI
1
SI
2
SI
3
SI
4
SI
5
SI
6
SI7
SI8
SI9
0
0
0
0
0
0
0
0
0
0
SI
0
SI
1
SI
2
SI
3
SI
4
SI
5
SI
6
SI
7
SI
8
SI
9
0
0
0
0
0
0
0
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