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參數(shù)資料
| 型號(hào)： | TMC2243 |
| 廠(chǎng)商： | Fairchild Semiconductor Corporation |
| 英文描述： | 10 x 10 Bit, 20 MHz CMOS FIR(Finite Impulse Response) Filter(10 x 10 位,20 MHz CMOS 有限脈沖響應(yīng)濾波器) |
| 中文描述： | 10 × 10位，20兆赫的CMOS FIR（有限沖擊響應(yīng)）濾波器（10 × 10位，20兆赫的CMOS有限脈沖響應(yīng)濾波器） |
| 文件頁(yè)數(shù)： | 3/16頁(yè) |
| 文件大小： | 120K |
| 代理商： | TMC2243 |
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PRODUCT SPECIFICATION
TMC2243
3
Pin Name
Power
V
DD
GND
Inputs
DI
9-0
Pin Number
Description
B1, K6, C10, C11
B2, K1, K10, B11
Supply Voltage.
Ground.
The TMC2243 operates from a single +5V supply.
F2, F1, G2, G1,
H2, H1, J2, J1,
K2, L2
Data Input.
MSB (sign bit) and Dl
representation, and is clocked into the data register on each rising edge of
clock. See Figure 1.
Sum Input.
SI
21
through SI
6
is the 16-bit Sum-In port. SI
bit). Sum-In is truncated to bit SI
6
(plus the 1/2 LSB rounding bit in SI
in two's complement representation. See Figure 1. The Sum-In port is
registered, on the rising edge of clock, only when FT
Unique input setup requirements must be observed when operating in the
feedthrough mode (FT
1
= HIGH) See text.
Coefficient Input.
CI
9
through CI
0
is the 10-bit registered Coefficient Input;
CI
9
is the MSB (sign bit) and CI
0
is the LSB. Each coefficient and its write
enable address (CWE
1-3
) are registered on the same clock. The coefficient is
then latched into the indicated register (C
clock. The contents of this bus are ignored if a coefficient register is not
selected (CWE = 00). The format of CI
DI
9
through DI
0
is the 10-bit registered Data Input; Dl
is the LSB. Data is in two's complement
9
is the
0
SI
21-6
L8, K9, L9, K11,
J10, J11, H10,
H11, G10, G11,
F10, F11, E10,
E11, D10, D11
21
is the MSB (sign
5
) and is
1
=LOW.
CI
9-0
K8, L7, K7, L6,
L5, K5, L4, K4,
L3, K3
1-3
) at the rising edge of the next
9-0
is identical to that of DI
9-0
.
Outputs
SO
21-6
A10, B9, A9, B8,
A8, B7, A7, B6,
A6, B5, A5, B4,
A4, B3, A3, A2
Sum Output.
port; SO
products and accumulations are 23 bits but Sum-Out is internally truncated to
16 bits, and excludes the overflow bit and the 6 LSBs. The format is identical
to that of SI
21-6
. See Figure 1.
SO
21
through SO
6
is the three-state 16-bit registered Sum-Out
is the MSB (sign bit). For maximum precision, the internal
21
Clock
CLK
L10
Master Clock.
CLK strobes all enabled registers. All timing specifications are referenced to
the rising edge of clock.
The TMC2243 has a single clock input. The rising edge of
Controls
CWE
1-0
E1, E2
Coefficient Write Enable.
Enable control indicate which of the coefficient registers is to receive a new
coefficient at the beginning of the next clock cycle.
CWE
1-0
Coefficient Register Selected
0 0
Holds all coefficients unchanged.
0 1
C
1
1 0
C
2
1 1
C
3
Feedthrough.
These registered Feed Through controls select clocked
(FT
i
= LOW) or feedthrough (FT
i
= HIGH) operation for each of the pipeline
registers. Setting FT
i
= LOW inserts a zero coefficient stage, or additional
register, before the ith non-zero stage.
Output Enable.
Output Enable is a registered three-state enable control
which forces the Sum-Out port and Overflow to the high-impedance state
when HIGH. These outputs are enabled when OE is LOW.
The two bits of the registered Coefficient Write
FT
3-1
D1, D2, C1
OE
C2
Flags
OV
B10
Overflow.
HIGH whenever the summation result exceeds 16 bits and is reset to LOW on
the next nonoverflowing result.
The Overflow Flag is a registered three-state output which goes
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