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參數(shù)資料
| 型號： | TMC1185 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | 10-Bit, 40 Msps Sampling Analog-to-Digital Converter(10位,采樣速率40Msps,A/D轉(zhuǎn)換器) |
| 中文描述： | 10位，40 Msps的采樣模擬到數(shù)字轉(zhuǎn)換器（10位，40Msps采樣速率，的A / D轉(zhuǎn)換器） |
| 文件頁數(shù)： | 3/20頁 |
| 文件大?。?/td> | 191K |
| 代理商： | TMC1185 |
PRODUCT SPECIFICATION
TMC1185
3
time-align it with the data created from the following
quantizer stages. This aligned data is fed into a digital error
correction circuit which can adjust the output data based on
the information found on the redundant bits. This technique
gives the TMC1185 excellent differential linearity and
guarantees no missing codes at the 10-bit level.
The output data is available in Straight Offset Binary (SOB)
or Binary Two’s Complement (BTC) format.
The Analog Input and Internal Reference
The analog input of the TMC1185 can be configured in
various ways and driven with different circuits, depending on
the nature of the signal and the level of performance desired.
The TMC1185 has an internal reference that sets the full
scale input range of the A/D. The differential input range has
each input centered around the common-mode of +2.25V,
with each of the two inputs having a full scale range of
+1.25V to +3.25V. Since each input is 2V peak-to-peak and
180
°
out of phase with the other, a 4V differential input
signal to the quantizer results. As shown in Figure 3, the
positive full scale reference (REFT) and the negative full
scale reference (REFB) are brought out for external bypass-
ing. In addition, the common-mode voltage (CM) may be
used as a reference to provide the appropriate offset for the
driving circuitry. However, care must be taken not to
appreciably load this reference node. For more information
regarding external references, single-ended inputs, and input
drive circuits, refer to the applications section.
Figure 3. Internal Reference Structure
Clock Requirements
The CLK pin accepts a CMOS level clock input. Both the
rising and falling edges of the externally applied clock
control the various interstage conversions in the pipeline.
Therefore, the clock signal’s jitter, rise/fall times and duty
cycle can affect conversion performance.
Low clock
frequency-domain signal environments.
Clock
rise and fall times
(<2ns for best performance).
For most applications, the clock duty should be set to
50%. However, for applications requiring no missing
codes, a slight skew in the duty cycle will improve DNL
performance for conversion rates >35MHz and input
frequencies <2MHz (see Timing Diagram). A possible
method for skewing the 50% duty cycle source is shown
in Figure 4.
jitter
is critical to SNR performance in
should be as short as possible
Figure 4. Clock Skew Circuit
Digital Output Data
The 10-bit output data is provided at CMOS logic levels.
There is a 6.5 clock cycle data latency from the start convert
signal to the valid output data. The standard output coding
is Straight Offset Binary where a full scale input signal
corresponds to all “1’s” at the output. This condition is met
with pin 19 “LO” or Floating due to an internal pull-down
resistor. By applying a high voltage to this pin, a Binary
Two’s Complement output will be provided where the most
significant bit is inverted. The digital outputs of the
TMC1185 can be set to a high impedance state by driving
OE (pin 18) with a logic “HI”. Normal operation is achieved
with pin 18 “LO” or Floating due to an internal pull-down
resistor. This function is provided for testability purposes
and is not meant to drive digital buses directly or be dynami-
cally changed during the conversion process.
+1.25V
+3.25V
2k
W
2k
W
0.1
μ
F
0.1
μ
F
+2.25V
65-1185-04
REFT
REFB
CM
TMC1185
To
Internal
Comparators
21
22
23
0.1
μ
F
R
V
2k
W
V
DD
0.1
μ
F
V
DD
CLK
OUT
CLK
65-1185-05
IN
IC2
IC1
IC1, IC2 = ACT04
R
V
= 220
W
, typical
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| TMC1203KLC40_Q | 功能描述:視頻模擬/數(shù)字化轉(zhuǎn)換器集成電路 Video a/D Converter Tripple 8Bit 4MSPS RoHS:否 制造商:Texas Instruments 輸入信號類型:Differential 轉(zhuǎn)換器數(shù)量:1 ADC 輸入端數(shù)量:4 轉(zhuǎn)換速率:3 Gbps 分辨率:8 bit 結(jié)構(gòu): 輸入電壓:3.3 V 接口類型:SPI 信噪比: 電壓參考: 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TCSP-48 封裝:Reel |
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