參數(shù)資料
型號: TMB2193MS100
廠商: Fairchild Semiconductor Corporation
英文描述: Demonstration Board for the TMC2193
中文描述: 演示板的TMC2193
文件頁數(shù): 22/24頁
文件大?。?/td> 167K
代理商: TMB2193MS100
TMB2193MS100
PRODUCT SPECIFICATION
22
P
Output Edge Connector Design Notes
1.
Boards with different revision letters may not be com-
patible; damage may occur if they are connected
together.
2.
XPXCK is a two times pixel clock fed BACKWARD.
3.
XHSYNC and XVSYNC are timing reference signals
fed BACKWARD.
4.
The MASTER/SLAVE signal states if a board is a
MASTER or a SLAVE board. This signal is fed FOR-
WARD. A MASTER board produces the PXCK,
HSYNC, and VSYNC signals, and a SLAVE board
expects to receive XPXCK, XHSYNC, XVSYNC, etc.
5.
XDIR is fed FORWARD and controls in which direction
the XRS[3:0] data flows.
6.
PGM_OUT negative going signal pulse for initiating
programming of down stream boards, generated once
the devices on the board have been programmed. Care
must be taken to ensure that multiple devices do not try
to drive the RBUS at any given time. The Minimum
width of PGM_OUT is 1uS.
7.
The RESET pin on the output edge connector should be
connected directly to the RESET pin on the input con-
nector. A link should be used to connect any pulse to the
RESET line.
8.
The MASTER/SLAVE, XDIR, PGM_OUT and RESET
pins on the output edge connector should be connected
to +5V through a 10k pull up resistor.
9.
The CLAMP signal is fed BACKWARD from a MAS-
TER to a SLAVE board. The CLAMP signal should not
be fed FORWARD.
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