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參數(shù)資料
| 型號： | TMB2193MS100 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Demonstration Board for the TMC2193 |
| 中文描述： | 演示板的TMC2193 |
| 文件頁數(shù)： | 2/24頁 |
| 文件大?。?/td> | 167K |
| 代理商： | TMB2193MS100 |
TMB2193MS100
PRODUCT SPECIFICATION
2
P
Functional Description
The TMB2193MS100 is designed to demonstrate the perfor-
mance of the TMC2193 Digital Video Encoder (DENC). For
a complete description of the TMC2193, please refer to the
TMC2193 data sheet. The TMB2193MS100 is compatible
with other Fairchild Demo boards. Typical configurations
are the TMC2067P7C, the TMC2068P7C, and the
TMB2193MS100 or the TMB0001MS100 and the
TMB2193MS100. The first configuration requires an analog
composite or S-video input and supplies a re-encoded analog
composite or S-video output. The later requires a parallel
D1 input and supplies an encoded analog composite or
S-video output.
The TMC2193 can be operated in D1, Genlock or Master
mode. In the D1 mode the synchronization is derived from
the TRS codes embedded in the D1 data stream. The
TMB2193MS100 has the TMC2072 Genlock front end,
which supplies the HSYNC, VSYNC and subcarrier infor-
mation to the TMC2193 for the Genlock operation of the
encoder. In Master mode the synchronization is driven by
the TMC2193, supplying the line (HSYNC) and field
(VSYNC or BnT) synchronization signals. With the
TMC2193 running in Master mode the TMB2193MS100
demo board interfaces directly to either a MPEG decoder or
a video framestore with no additional glue logic.
The TMB2193MS100 has an onboard microcontroller
(MCU) to program the TMC2193, the TMC2072, and to
configure the FPGA. All the default register maps are held
within the MCU. Table 1 provides a description of each of
the default register maps. A control register map is written to
the TMC2193, the TMC2072, and to Port 2 of the MCU each
time the MRST\ button is pressed. The MCU determines
which map to load from the PROG[3-0] (Px) dip switches.
The TMC2193, 2072 and the MCU can also be driven by the
Raydemo software. The interface is provided by the RBUS
connector on the TMB2193MS100 and the TMC2070P7C
R-Bus interface board. With this setup the user can config-
ure the TMC2193, the TMC2072 and the MCU with any
IBM compatible PC.
Table 1. Default Control Register Maps
P3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
P2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
P1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
P0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Format
NTSC
NTSC
NTSC
NTSC
NTSC
NTSC
NTSC
NTSC
PAL
PAL
PAL
PAL
PAL
PAL
PAL
PAL
Mode
MASTER
MASTER
MASTER
D1
D1
D1
Genlock
Genlock
MASTER
MASTER
MASTER
D1
D1
D1
Genlock
Genlock
Source
Mod. Ramp
75% CB
100% CB
D1
D1
D1
601
601
Mod. Ramp
75% CB
100% CB
D1
D1
D1
601
601
Output Mode
Composite, S-Video
Composite, YPBPR
Composite, RGB
Composite, YPBPR
Composite, RGB
DCVBS
Composite, YPBPR
Composite, RGB
Composite, S-Video
Composite, YPBPR
Composite, RGB
Composite, YPBPR
Composite, RGB
DCVBS
Composite, YPBPR
Composite, RGB
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