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參數(shù)資料
| 型號： | TMB2193MS100 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Demonstration Board for the TMC2193 |
| 中文描述： | 演示板的TMC2193 |
| 文件頁數(shù)： | 20/24頁 |
| 文件大小： | 167K |
| 代理商： | TMB2193MS100 |
TMB2193MS100
PRODUCT SPECIFICATION
20
P
Input Edge Connector Design Notes
1.
Boards with different revision letters may not be
compatible. Damage may occur if they are con-
nected together!
2.
XPXCK is a two times pixel clock fed BACKWARD.
3.
XHSYNC and XVSYNC are timing reference signals
fed BACKWARD.
4.
The MASTER/SLAVE signal states if a board is a
MASTER or a SLAVE board. This signal is fed
FORWARD. A MASTER board produces the PXCK,
HSYNC, and VSYNC signals, and a SLAVE board
expects to receive XPXCK, XHSYNC, XVSYNC, etc.
5.
XDIR is fed FORWARD and controls in which direction
the XRS[3:0] data flows.
6.
PGM_IN is a negative going pulse, logically ANDed
with the onboard program start pulse, for initiating the
programming sequence for components on that board.
Care must be taken to ensure that multiple devices do
not try to drive the RBUS at any given time. Minimum
width of PGM_IN is 1uS.
7.
The RESET pin on the input edge connector should be
connected directly to the RESET pin on the output con-
nector. A link should be used to connect any pulse to the
RESET line.
8.
The MASTER/SLAVE, XDIR, PGM_IN and RESET
pins on the input edge connector should be connected to
+5V through a 10k pull up resistor.
9.
The CLAMP signal is fed BACKWARD from a
MASTER to a SLAVE board. The CLAMP signal
should not be fed FORWARD.
Y/Composite
LPF and
Clamp Circuit
Chrominance
BPF and
Clamp Circuit
T
T
SW1
SW1
+5V 0V -5V
2
65-B2193-14
10 bit
ADCs
Digital
LPFs
TMC2242
EPROM
FPGA
Signal Flow FORWARD
TMC2072
TMC3003
Low Quality
LPF
Low Quality
LPF
Low Quality
LPF
H
L
H
L
H
L
TMC22153
DC Supply
Decoder
Input Logic
TMC2242
1
32
1
32
1
32
1
32
SW2
Signal Flow BACKWARD
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