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| 型號： | TLV320DAC32IRHBTG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | DAC |
| 英文描述： | SERIAL INPUT LOADING, DAC WITH PROGRAMMABLE PLL, PQCC32 |
| 封裝： | 5 X 5 MM, GREEN, PLASTIC, QFN-32 |
| 文件頁數(shù)： | 68/69頁 |
| 文件大?。?/td> | 1242K |
| 代理商： | TLV320DAC32IRHBTG4 |
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TIMING CHARACTERISTICS
(1)
ts(DI)
th(DI)
WCLK
BCLK
SDIN
td(WS)
TIMING CHARACTERISTICS
(1)
th(WS)
ts(WS)
ts(DI)
th(DI)
WCLK
BCLK
SDIN
tL(BCLK)
tH(BCLK)
tP(BCLK)
TIMING CHARACTERISTICS
(1)
SLAS506B – NOVEMBER 2006 – REVISED DECEMBER 2008........................................................................................................................................ www.ti.com
All specifications typical at 25C, DVDD = 1.8 V
IOVDD = 1.1 V
IOVDD = 3.3 V
PARAMETER
UNIT
MIN
MAX
MIN
MAX
td (WS)
WCLK delay time
50
15
ns
ts(DI)
DIN setup time
10
6
ns
th(DI)
DIN hold time
10
6
ns
tr
Rise time
30
10
ns
tf
Fall time
30
10
ns
(1)
All timing specifications are measured at characterization but not tested at final test.
Figure 2. DSP Timing in Master Mode
All specifications typical at 25C, DVDD = 1.8 V
IOVDD = 1.1 V
IOVDD = 3.3 V
PARAMETER
UNIT
MIN
MAX
MIN
MAX
td (WS)
WCLK delay time
50
15
ns
ts(DI)
DIN setup time
10
6
ns
th(DI)
DIN hold time
10
6
ns
tr
Rise time
30
10
ns
tf
Fall time
30
10
ns
(1)
All timing specifications are measured at characterization but not tested at final test.
Figure 3. I2S/LJF/RJF Timing in Slave Mode
All specifications typical at 25C, DVDD = 1.8 V
(1)
All timing specifications are measured at characterization but not tested at final test.
8
Copyright 2006–2008, Texas Instruments Incorporated
Product Folder Link(s): TLV320DAC32
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