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參數(shù)資料
| 型號： | TLV320DAC32IRHBTG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | DAC |
| 英文描述： | SERIAL INPUT LOADING, DAC WITH PROGRAMMABLE PLL, PQCC32 |
| 封裝： | 5 X 5 MM, GREEN, PLASTIC, QFN-32 |
| 文件頁數(shù)： | 35/69頁 |
| 文件大小： | 1242K |
| 代理商： | TLV320DAC32IRHBTG4 |
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SLAS506B – NOVEMBER 2006 – REVISED DECEMBER 2008........................................................................................................................................ www.ti.com
Page 0 / Register 8:
Audio Serial Data Interface Control Register A
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7
R/W
0
Bit Clock Directional Control
0: Bit clock is an input (slave mode)
1: Bit clock is an output (master mode)
D6
R/W
0
Word Clock Directional Control
0: Word clock is an input (slave mode)
1: Word clock is an output (master mode)
D5
R/W
0
Reserved. Only write zero this bit.
D4
R/W
0
Bit/ Word Clock Drive Control
0:
Bit clock and word clock will not be transmitted when in master mode if DAC is powered down
1:
Bit clock and word clock will continue to be transmitted when in master mode, even if DAC is
powered down
D3
R/W
0
Reserved. Only write zero to this bit.
D2
R/W
0
3-D Effect Control
0: Disable 3-D digital effect processing
1: Enable 3-D digital effect processing
D1-D0
R/W
00
Reserved. Only write zeroes to these bits.
Page 0 / Register 9:
Audio Serial Data Interface Control Register B
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7–D6
R/W
00
Audio Serial Data Interface Transfer Mode
00: Serial data bus uses I2S mode
01: Serial data bus uses DSP mode
10: Serial data bus uses right-justified mode
11: Serial data bus uses left-justified mode
D5–D4
R/W
00
Audio Serial Data Word Length Control
00: Audio data word length = 16-bits
01: Audio data word length = 20-bits
10: Audio data word length = 24-bits
11: Audio data word length = 32-bits
D3
R/W
0
Bit Clock Rate Control in master mode only
This register only has effect when bit clock is programmed as an output
0: Continuous-transfer mode used to determine master mode bit clock rate
1: 256-clock transfer mode used, resulting in 256 bit clocks per frame
D2
R/W
0
DAC Re-Sync
0: Don’t Care
1:
Re-Sync Stereo DAC with Digital Interface if the group delay changes by more than DACFS/4.
D1
R/W
0
Reserved. Only write zero to this bit.
D0
R/W
Re-Sync Mute Behavior
0: Re-Sync is done without soft-muting the channel. (DAC)
1: Re-Sync is done by internally soft-muting the channel. (DAC)
40
Copyright 2006–2008, Texas Instruments Incorporated
Product Folder Link(s): TLV320DAC32
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