參數(shù)資料
型號： TLV320DAC32IRHBTG4
廠商： TEXAS INSTRUMENTS INC
元件分類： DAC
英文描述： SERIAL INPUT LOADING, DAC WITH PROGRAMMABLE PLL, PQCC32
封裝： 5 X 5 MM, GREEN, PLASTIC, QFN-32
文件頁數(shù)： 58/69頁
文件大?。?/td> 1242K
代理商： TLV320DAC32IRHBTG4
www.ti.com........................................................................................................................................ SLAS506B – NOVEMBER 2006 – REVISED DECEMBER 2008
Page 1 / Register 47:
Right Channel De-emphasis Filter N0 Coefficient MSB Register
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7-D0
R/W
00111001
Right Channel De-emphasis Filter N0 Coefficient MSB The 16-bit integer contained in the MSB
and LSB registers for this coefficient are interpreted as a 2’s complement integer, with possible
values ranging from –32768 to +32767.
Page 1 / Register 48:
Right Channel De-emphasis Filter N0 Coefficient LSB Register
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7-D0
R/W
01010101
Right Channel De-emphasis Filter N0 Coefficient LSB The 16-bit integer contained in the MSB and
LSB registers for this coefficient are interpreted as a 2’s complement integer, with possible values
ranging from –32768 to +32767.
Page 1 / Register 49:
Right Channel De-emphasis Filter N1 Coefficient MSB Register
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7-D0
R/W
11110011
Right Channel De-emphasis Filter N1 Coefficient MSB The 16-bit integer contained in the MSB
and LSB registers for this coefficient are interpreted as a 2’s complement integer, with possible
values ranging from –32768 to +32767.
Page 1 / Register 50:
Right Channel De-emphasis Filter N1 Coefficient LSB Register
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7-D0
R/W
00101101
Right Channel De-emphasis Filter N1 Coefficient LSB The 16-bit integer contained in the MSB and
LSB registers for this coefficient are interpreted as a 2’s complement integer, with possible values
ranging from –32768 to +32767.
Page 1 / Register 51:
Right Channel De-emphasis Filter D1 Coefficient MSB Register
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7-D0
R/W
01010011
Right Channel De-emphasis Filter D1 Coefficient MSB The 16-bit integer contained in the MSB
and LSB registers for this coefficient are interpreted as a 2’s complement integer, with possible
values ranging from –32768 to +32767.
Page 1 / Register 52:
Right Channel De-emphasis Filter D1 Coefficient LSB Register
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7-D0
R/W
01111110
Right Channel De-emphasis Filter D1 Coefficient LSB The 16-bit integer contained in the MSB and
LSB registers for this coefficient are interpreted as a 2’s complement integer, with possible values
ranging from –32768 to +32767.
Page 1 / Register 53:
3-D Attenuation Coefficient MSB Register
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7-D0
R/W
01111111
3-D Attenuation Coefficient MSB The 16-bit integer contained in the MSB and LSB registers for
this coefficient are interpreted as a 2’s complement integer, with possible values ranging from
–32768 to +32767.
Page 1 / Register 54:
3-D Attenuation Coefficient LSB Register
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7-D0
R/W
11111111
3-D Attenuation Coefficient LSB The 16-bit integer contained in the MSB and LSB registers for this
coefficient are interpreted as a 2’s complement integer, with possible values ranging from –32768
to +32767.
Copyright 2006–2008, Texas Instruments Incorporated
61
Product Folder Link(s): TLV320DAC32
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