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參數(shù)資料
| 型號： | TLV320DAC3202IYZJT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 音頻控制 |
| 英文描述： | VOLUME CONTROL CIRCUIT, PBGA20 |
| 封裝： | 2 X 2.50 MM, 0.50 MM PITCH, WCSP-20 |
| 文件頁數(shù)： | 5/20頁 |
| 文件大?。?/td> | 435K |
| 代理商： | TLV320DAC3202IYZJT |
www.ti.com
SLAS726A – SEPTEMBER 2010 – REVISED JANUARY 2011
Dual Supply Charge Pump
The charge pump on TLV320DAC3202 has dual-supply capability module with automatic selection which can be
either from VBAT or VIO depending on the input signal range and load current that is detected. Charge pump
generates both the positive and negative rails for low and high headset rails. For typical listening range where
the signal level is low, the supply is expected to be from VIO and headset rail is 0.9 V. For higher signal levels
where higher current drains from VIO are not possible, the IC uses an automatic input voltage and load current
threshold based algorithm to switch ON the VPOW regulator and use VPOW, which is powered from VBAT. It is
designed to power the left and right headset drivers up to rated full scale output.
The threshold point to transition between the low and high power range can be programmed through I2C
interface. There are two threshold points controlled by register bits, one for each of left and right channels. The
threshold monitor mechanisms for each channel can be independently enabled and programmed. The load
current threshold settings can be 10.5 mA, 11.5 mA, 12.5 mA (default) or 13.5 mA per channel.
Output Impedance
In order to share the output connector between audio and other signals such as video output, a high impedance
option is implemented that can be enabled through I2C controller. In this mode the output impedance is increased
while the signal is muted. As shown in below table the output impedance is large enough to avoid an unwanted
attenuation of other signal connected to the jack contact.
Table 9. Output Impedance in Various Mode Settings
CHIP_EN
HiZ
HS_EN
IMPEDANCE
MODE
0
150
Ω
Shut down
0
1
150
Ω
Shut down
8.5
Ω at 40 kHz
0
1
0
600
Ω at 6 MHz
HiZ
400
Ω at 13 MHz
0
1
-
Invalid
1
0
150
Ω
Active, HS off
1
0
1
-
Active
1
0
-
Invalid
1
-
Invalid
I
2C INTERFACE
The control interface for programming the registers on TLV320DAC3202 is done using a standard I2C interface
with the IC operating in slave mode. The 2 modes of operation as defined in Ref [1,2] are (a) Standard-mode up
to 100 kbit/s, and (b) Fast-mode up to 400 kbit/s. The IC defaults to fast-mode. A 7-bit slave addressing is used.
The device I2C slave address is fixed to 0011010X, with 00110100 for master write cycle (TLV320DAC3202
reads) and 00110101 for master read cycle (TLV320DAC3202 writes). For data and clock lines, pull up resistors
are required and are expected to be provided as defined in section 7 of Ref [1].
References
[1] UM10204: I2C-Bus Specification and user manual Rev. 03 – 19 June 2007
[2] The I2C-BUS SPECIFICATION VER 2.1 January 2000
[3] I2S Bus specification, Phillips Semiconductors, June 1996
Copyright 2010–2011, Texas Instruments Incorporated
13
Product Folder Link(s): TLV320DAC3202
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| TLV320DAC3203 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Ultra Low Power Stereo Audio Codec With Integrated Headphone Amplifiers |
| TLV320DAC3203EVM-K | 功能描述:音頻 IC 開發(fā)工具 TLV320DAC3203 Eval Mod RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評估:TAS5614L 工作電源電壓:12 V to 38 V |
| TLV320DAC3203IRGER | 功能描述:接口—CODEC Ultra Low Pwr Stereo Audio Codec RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TLV320DAC3203IRGET | 功能描述:接口—CODEC Ultra Low Pwr Stereo Audio Codec RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
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