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參數(shù)資料
| 型號： | TLV320DAC3202IYZJT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 音頻控制 |
| 英文描述： | VOLUME CONTROL CIRCUIT, PBGA20 |
| 封裝： | 2 X 2.50 MM, 0.50 MM PITCH, WCSP-20 |
| 文件頁數(shù)： | 4/20頁 |
| 文件大小： | 435K |
| 代理商： | TLV320DAC3202IYZJT |
AVDD
DVDD (1.8V)
Start up Time
Wake up Time
15.5ms
3ms
T1 > 0
1ms
CHIP_EN = 1
HSL/R_EN = 1
Standby State
Active State
SLAS726A – SEPTEMBER 2010 – REVISED JANUARY 2011
www.ti.com
Table 8. Volume Control Register Decoding (continued)
REGISTER VALUE
GAIN (dB)
GAIN_ANALOG (dB)
GAIN_DIGITAL (dB)
10
-23
-12
-11
9
-25
-12
-13
8
-27
-12
-15
7
-31
-12
-19
6
-35
-12
-23
5
-39
-12
-27
4
-43
-12
-31
3
-47
-12
-35
2
-51
-12
-39
1
-55
-12
-43
0
-59
-12
-47
SYSTEM AND CONTROL
Power-Up Sequence
The power up sequence of the IC is initiated by asserting the CHIP_EN bit to logic ‘1’. It is expected that VBAT
and VIO are powered up prior to assertion of this bit. The HSL/R amplifiers are then enabled by writing to their
perspective control bits in register address 0x01. The I2S clock must be present prior to power up sequence and
maintain its activity during active mode. The figure below shows the typical power up sequence of the IC. The IC
power up state machine updates I2C register bits corresponding to enabled modules. I2C register control can
subsequently be used to turn OFF unused circuits.
The power down sequence is initiated by de-asserting the CHIP_EN bit in CODEC_EN register. It is expected
that the CHIP_EN bit is de-asserted prior to turning OFF the VIO supply.
The HS driver power on/off sequence is designed to be click-pop free.
Figure 12. Power-Up Sequence Timing
12
Copyright 2010–2011, Texas Instruments Incorporated
Product Folder Link(s): TLV320DAC3202
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