參數(shù)資料
型號(hào)： TLV320DAC3202IYZJT
廠商： TEXAS INSTRUMENTS INC
元件分類： 音頻控制
英文描述： VOLUME CONTROL CIRCUIT, PBGA20
封裝： 2 X 2.50 MM, 0.50 MM PITCH, WCSP-20
文件頁(yè)數(shù)： 19/20頁(yè)
文件大?。?/td> 435K
代理商： TLV320DAC3202IYZJT
SLAS726A – SEPTEMBER 2010 – REVISED JANUARY 2011
www.ti.com
DIGITAL INTERFACE
Audio Interface
The audio interface for data communication with application processor or modem supports multiple formats such
as I2S, left justified, right justified or the short frame sync PCM formats. The default interface format is I2S at
48-kHz sampling rate and 16-bit data size. The clock input selection module within PLL block also supports
multiple input frequency options. The input clock must be in standard square wave format; hence a clock squarer
is not necessary. The following tables shows the details of audio interface configuration through I2C register
controls.
Table 4. Audio Interface Format Configuration Register
INTF_MODE (1:0)
INTERFACE FORMAT TYPE
0
Standard I2S
0
1
Left justified I2S
1
0
Right justified I2S
1
Short PCM
Table 5. Audio Interface BCLK to WCLK Ratio Setting Register
INTERFACE FRAME SIZE,
INTF_FRAME_SIZE (2:0)
INTF_SIZE (1:0)
BCLK/WCLK
0
2 x 16 x Fs
0
1
0
1
2 x 20 x Fs
0
1
0
1
0
2 x 24 x Fs
0
1
2 x 32 x Fs
1
0
4 x 16 x Fs
1
0
1
0
1
4 x 20 x Fs
1
0
1
0
4 x 24 x Fs
1
4 x 32 x Fs
Table 6. Audio Sampling Rate Setting Register
CLK_MODE(3:0)
INTERFACE SAMPLING RATE, WCLK (kHz)
0
8
0
1
11.025
0
1
0
12
0
1
NA
0
1
0
16
0
1
0
1
22.05
0
1
0
24
0
1
NA
1
0
32
1
0
1
44.1
1
0
1
0
48
1
0
1
NA
1
0
NA
Table 7. Detailed Configuration of Interface Including PLL Setup Registers
BCLK/WCLK
DATA SIZE
Fs (WCLK)
Fs x DATA
BCLK/PLL INPUT
32
16
48.000
1536
40
20
48.000
1920
48
24
48.000
2304
8
Copyright 2010–2011, Texas Instruments Incorporated
Product Folder Link(s): TLV320DAC3202
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