參數(shù)資料
型號(hào)： TLV320DAC3120IRHBR
廠商： TEXAS INSTRUMENTS INC
元件分類： DAC
英文描述： SERIAL INPUT LOADING, 24-BIT DAC, PQCC32
封裝： 5 X 5 MM, PLASTIC, QFN-32
文件頁(yè)數(shù)： 58/110頁(yè)
文件大小： 1230K
代理商： TLV320DAC3120IRHBR
DA(6)
DA(0)
RA(7)
RA(0)
D(7)
D(0)
Start
(M)
7-bitDevice Address
(M)
Write
(M)
Slave
Ack
(S)
8-bitRegister Address
(M)
Slave
Ack
(S)
8-bitRegisterData
(M)
Stop
(M)
Slave
Ack
(S)
SDA
SCL
(M)=>SDA ControlledbyMaster
(S)=>SDA ControlledbySlave
www.ti.com
SLAS659 – NOVEMBER 2009
Communication on the I2C bus always takes place between two devices, one acting as the master and the
other acting as the slave. Both masters and slaves can read and write, but slaves can only do so under
the direction of the master. Some I2C devices can act as masters or slaves, but the TLV320DAC3120 can
only act as a slave device.
An I2C bus consists of two lines, SDA and SCL. SDA carries data, and the SCL signal provides the clock.
All data is transmitted across the I2C bus in groups of eight bits. To send a bit on the I2C bus, the SDA line
is driven to the appropriate level while SCL is LOW (a LOW on SDA indicates the bit is 0, while a HIGH
indicates the bit is 1).
Once the SDA line has settled, the SCL line is brought HIGH, then LOW. This pulse on the SCL line
clocks the SDA bit into the receiver shift register.
The I2C bus is bidirectional: the SDA line is used both for transmitting and receiving data. When a master
reads from a slave, the slave drives the data line; when a master sends to a slave, the master drives the
data line.
Most of the time the bus is idle, no communication is taking place, and both lines are HIGH. When
communication is taking place, the bus is active. Only master devices can start communication on the bus.
Normally, the data line is only allowed to change state while the clock line is LOW. If the data line changes
state while the clock line is HIGH, it is either a START condition or its counterpart, a STOP condition. A
START condition is when the clock line is HIGH and the data line goes from HIGH to LOW. A STOP
condition is when the clock line is HIGH and the data line goes from LOW to HIGH.
After the master issues a START condition, it sends a byte that selects the slave device for
communication. This byte is called the address byte. Each device on an I2C bus has a unique 7-bit
address to which it responds. (Slaves can also have 10-bit addresses; see the I2C specification for
details.) The master sends an address in the address byte, together with a bit that indicates whether it
wishes to read from or write to the slave device.
Every byte transmitted on the I2C bus, whether it is address or data, is acknowledged with an
acknowledge bit. When a master has finished sending a byte (8 data bits) to a slave, it stops driving SDA
and waits for the slave to acknowledge the byte. The slave acknowledges the byte by pulling SDA LOW.
The master then sends a clock pulse to clock the acknowledge bit. Similarly, when a master has finished
reading a byte, it pulls SDA LOW to acknowledge this to the slave. It then sends a clock pulse to clock the
bit. (Remember that the master always drives the clock line.)
A not-acknowledge is performed by simply leaving SDA HIGH during an acknowledge cycle. If a device is
not present on the bus, and the master attempts to address it, it will receive a not-acknowledge because
no device is present at that address to pull the line LOW.
When a master has finished communicating with a slave, it may issue a STOP condition. When a STOP
condition is issued, the bus becomes idle again. A master may also issue another START condition. When
a START condition is issued while the bus is active, it is called a repeated START condition.
The TLV320DAC3120 can also respond to and acknowledge a general call, which consists of the master
issuing a command with a slave address byte of 00h. This feature is disabled by default, but can be
enabled via page 0 / register 34, bit D5.
Figure 5-30. I2C Write
Copyright 2009, Texas Instruments Incorporated
APPLICATION INFORMATION
51
Product Folder Link(s): TLV320DAC3120
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