參數(shù)資料
型號： TLV320DAC3120IRHBR
廠商： TEXAS INSTRUMENTS INC
元件分類： DAC
英文描述： SERIAL INPUT LOADING, 24-BIT DAC, PQCC32
封裝： 5 X 5 MM, PLASTIC, QFN-32
文件頁數(shù)： 20/110頁
文件大小： 1230K
代理商： TLV320DAC3120IRHBR
www.ti.com
SLAS659 – NOVEMBER 2009
5.2
Overview
The TLV320DAC3120 is a highly integrated mono audio DAC for portable computing, communication, and
entertainment applications. A register-based architecture eases integration with microprocessor-based
systems through standard serial-interface buses. This device contains a two-wire I2C bus interface, which
allows full register access. All peripheral functions are controlled through these registers and the onboard
state machines.
The TLV320DAC3120 consists of the following blocks:
miniDSP digital signal-processing block
Audio DAC
Dynamic range compressor (DRC)
Mono headphone/lineout amplifier
Class-D mono amplifier capable of driving 4-
Ω or 8- speakers
Pin-controlled or register-controlled volume level
Power-down de-pop and power-up soft start
Analog inputs
I2C control interface
Power-down control block
Following a toggle of the RESET pin or a software reset, the device operates in the default mode. The I2C
interface is used to write to the control registers to configure the device.
The I2C address assigned to the TLV320DAC3120 is 001 1000. This device always operates in an I2C
slave mode. All registers are 8-bit, and all writable registers have readback capability. The device
auto-increments to support sequential addressing and can be used with I2C fast mode. Once the device is
reset, all appropriate registers are updated by the host processor to configure the device as needed by the
user.
5.2.1
Device Initialization
5.2.1.1
Reset
The TLV320DAC3120 internal logic must be initialized to a known condition for proper device function. To
initialize the device to its default operating condition, the hardware reset pin (RESET) must be pulled low
for at least 10 ns. For this initialization to work, both the IOVDD and DVDD supplies must be powered up.
It is recommended that while the DVDD supply is being powered up, the RESET pin be pulled low.
The device can also be reset via software reset. Writing a 1 into page 0 / register 1, bit D0 resets the
device.
5.2.1.2
Device Start-Up Lockout Times
After the TLV320DAC3120 is initialized through hardware reset at power-up or software reset, the internal
memories are initialized to default values. This initialization takes place within 1 ms after pulling the
RESET signal high. During this initialization phase, no register-read or register-write operation should be
performed on the DAC coefficient buffers. Also, no block within the codec should be powered up during
the initialization phase.
5.2.1.3
PLL Start-Up
Whenever the PLL is powered up, a start-up delay of approximately of 10 ms occurs after the power-up
command of the PLL and before the clocks are available to the codec. This delay is to ensure stable
operation of the PLL and clock-divider logic.
Copyright 2009, Texas Instruments Incorporated
APPLICATION INFORMATION
17
Product Folder Link(s): TLV320DAC3120
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