參數(shù)資料
型號(hào)： TLV320DAC3120IRHBR
廠商： TEXAS INSTRUMENTS INC
元件分類： DAC
英文描述： SERIAL INPUT LOADING, 24-BIT DAC, PQCC32
封裝： 5 X 5 MM, PLASTIC, QFN-32
文件頁(yè)數(shù)： 48/110頁(yè)
文件大?。?/td> 1230K
代理商： TLV320DAC3120IRHBR
÷ M
GPIO1 (CLKOUT)
CDIV_CLKIN
MCLK
BCLK
DIN
PLL_CLK
DAC_CLK
DAC_MOD_CLK
M = 1, 2, ..., 127, 128
B0363-01
PLL_CLKIN R J.D
PLL_CLK
P
=
SLAS659 – NOVEMBER 2009
www.ti.com
Figure 5-18. General-Purpose Clock Output Options
Table 5-21. Maximum TLV320DAC3120 Clock Frequencies
Clock
DVDD
≥ 1.65 V
CODEC_CLKIN
≤ 110 MHz
DAC_CLK (DAC DSP clock)
≤ 49.152 MHz
DAC_miniDSP_CLK
≤ 49.152MHz with DRC disabled
≤ 48 MHz with DRC enabled
DAC_MOD_CLK
6.758 MHz
DAC_fS
0.192 MHz
BDIV_CLKIN
55 MHz
CDIV_CLKIN
100 MHz when M is odd
110 MHz when M is even
5.7.1
PLL
For lower power consumption, it is best to derive the internal audio processing clocks using the simple
dividers. When the input MCLK or other source clock is not an integer multiple of the audio processing
clocks, then it is necessary to use the on-board PLL. The TLV320DAC3120 fractional PLL can be used to
generate an internal master clock used to produce the processing clocks needed by the DAC and
miniDSP. The programmability of this PLL allows operation from a wide variety of clocks that may be
available in the system.
The PLL input supports clocks varying from 512 kHz to 20 MHz and is register programmable to enable
generation of required sampling rates with fine resolution. The PLL can be turned on by writing to page 0 /
register 5, bit D7. When the PLL is enabled, the PLL output clock PLL_CLK is given by the following
equation:
(6)
where
R = 1, 2, 3, ..., 16 (page 0 / register 5, default value = 1)
J = 1, 2, 3, …, 63, (page 0 / register 6, default value = 4)
D = 0, 1, 2, …, 9999 (page 0 / register 7 and 8, default value = 0)
P = 1, 2, 3, …, 8 (page 0 / register 5, default value = 1)
42
APPLICATION INFORMATION
Copyright 2009, Texas Instruments Incorporated
Product Folder Link(s): TLV320DAC3120
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