參數(shù)資料
型號： TLV320AIC36IZQE
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PBGA80
封裝： 5 X 5 MM, GREEN, PLASTIC, VFBGA-80
文件頁數(shù)： 165/165頁
文件大?。?/td> 1895K
代理商： TLV320AIC36IZQE
www.ti.com
SBAS387A – MAY 2009 – REVISED JUNE 2010
6.2.58 Page 0 / Register 61:
ADC Signal Processing Block Control Register
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D5
R
000
Reserved. Write only default values
D4–D0
R/W
0 0001
0 0000: The ADC miniDSP will be used for signal processing
0 0001: ADC Singal Processing Block PRB_R1
0 0010: ADC Signal Processing Block PRB_R2
0 0011: ADC Signal Processing Block PRB_R3
0 0100: ADC Signal Processing Block PRB_R4
…
1 0001: ADC Signal Processing Block PRB_R17
1 0010: ADC Signal Processing Block PRB_R18
1 0010-1 1111: Reserved. Do not use
6.2.59 Page 0 / Register 62:
ADC and DAC miniDSP Configuration Register
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7
R
0
Reserved. Write only default values
D6
R/W
0
ADC miniDSP Auxilliary Control Bit-A. Used for conditional instruction like JMP.
D5
R/W
0
ADC miniDSP Auxilliary Control Bit-B. Used for conditional instruction like JMP.
D4
R/W
0
0: Reset ADC miniDSP instruction counter at the start of new frame.
1: Do not reset ADC miniDSP instruction counter at the start of new frame. If ADC miniDSP is used
for Signal Processing
D3
R
0
Reserved. Write only default values
D2
R/W
0
DAC miniDSP Auxilliary Control Bit-A. Used for conditional instruction like JMP.
D1
R/W
0
DAC miniDSP Auxilliary Control Bit-B. Used for conditional instruction like JMP.
D0
R/W
0
0: Reset DAC miniDSP instruction counter at the start of new frame.
1: Do not reset DAC miniDSP instruction counter at the start of new frame. If DAC miniDSP is used
for Signal Processing
6.2.60 Page 0 / Register 63:
DAC Channel Setup Register 1
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7
R/W
0
Left DAC Channel Power Control
0: Left DAC Channel Powered Down
1: Left DAC Channel Powered Up
D6
R/W
0
Right DAC Channel Power Control
0: Right DAC Channel Powered Down
1: Right DAC Channel Powered Up
D5–D4
R/W
01
Left DAC Data path Control
00: Left DAC data is disabled
01: Left DAC data Left Channel Audio Interface Data
10: Left DAC data is Right Channel Audio Interface Data
11: Left DAC data is Mono Mix of Left and Right Channel Audio Interface Data
D3–D2
R/W
01
Right DAC Data path Control
00: Right DAC data is disabled
01: Right DAC data Right Channel Audio Interface Data
10: Right DAC data is Left Channel Audio Interface Data
11: Right DAC data is Mono Mix of Left and Right Channel Audio Interface Data
D1–D0
R/W
00
DAC Channel Volume Control's Soft-Step control
00: Soft-Stepping is 1 step per 1 DAC Word Clock
01: Soft-Stepping is 1 step per 2 DAC Word Clocks
10: Soft-Stepping is disabled
11: Reserved. Do not use
Copyright 2009–2010, Texas Instruments Incorporated
REGISTER MAP
99
Product Folder Link(s): TLV320AIC36
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